forked from M-Labs/artiq-zynq
merge control.rs into kernel.rs
This commit is contained in:
parent
105eb7c2bc
commit
6c18e24418
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@ -18,11 +18,9 @@ use libboard_zynq::{
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},
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};
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use libsupport_zynq::alloc::{vec, vec::Vec};
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use libcortex_a9::sync_channel;
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use libasync::{smoltcp::{Sockets, TcpStream}, task};
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use crate::kernel;
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use crate::control::KernelControl;
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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@ -143,7 +141,7 @@ async fn send_header(stream: &TcpStream, reply: Reply) -> Result<()> {
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Ok(())
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}
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async fn handle_connection(stream: TcpStream, control: Rc<RefCell<Option<KernelControl>>>) -> Result<()> {
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async fn handle_connection(stream: TcpStream, control: Rc<RefCell<Option<kernel::Control>>>) -> Result<()> {
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expect(&stream, b"ARTIQ coredev\n").await?;
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loop {
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expect(&stream, &[0x5a, 0x5a, 0x5a, 0x5a]).await?;
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@ -172,7 +170,7 @@ async fn handle_connection(stream: TcpStream, control: Rc<RefCell<Option<KernelC
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.take()
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.map(|control| control.reset());
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*control.borrow_mut() = Some(KernelControl::start(8192));
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*control.borrow_mut() = Some(kernel::Control::start(8192));
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}
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_ => return Err(Error::UnrecognizedPacket)
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}
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@ -219,7 +217,7 @@ pub fn main() {
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Sockets::init(32);
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let control: Rc<RefCell<Option<KernelControl>>> = Rc::new(RefCell::new(None));
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let control: Rc<RefCell<Option<kernel::Control>>> = Rc::new(RefCell::new(None));
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task::spawn(async move {
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loop {
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@ -1,38 +0,0 @@
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use alloc::{vec, vec::Vec};
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use libcortex_a9::{mutex::Mutex, sync_channel::{self, sync_channel}};
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use libsupport_zynq::boot::Core1;
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pub static CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<usize>>> = Mutex::new(None);
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pub static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<usize>>> = Mutex::new(None);
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/// Interface for core 0 to control core 1 start and reset
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pub struct KernelControl {
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core1: Core1<Vec<u32>>,
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pub tx: sync_channel::Sender<usize>,
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pub rx: sync_channel::Receiver<usize>,
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}
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impl KernelControl {
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pub fn start(stack_size: usize) -> Self {
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let stack = vec![0; stack_size / 4];
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let core1 = Core1::start(stack);
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let (core0_tx, core1_rx) = sync_channel(4);
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let (core1_tx, core0_rx) = sync_channel(4);
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*CHANNEL_0TO1.lock() = Some(core1_rx);
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*CHANNEL_1TO0.lock() = Some(core1_tx);
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KernelControl {
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core1,
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tx: core0_tx,
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rx: core0_rx,
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}
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}
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pub fn reset(self) {
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*CHANNEL_0TO1.lock() = None;
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*CHANNEL_1TO0.lock() = None;
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self.core1.reset();
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}
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}
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@ -1,11 +1,63 @@
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use libcortex_a9::sync_channel;
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use alloc::{vec, vec::Vec};
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use libcortex_a9::{mutex::Mutex, sync_channel::{self, sync_channel}};
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use libboard_zynq::println;
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use libsupport_zynq::boot::Core1;
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static CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<usize>>> = Mutex::new(None);
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static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<usize>>> = Mutex::new(None);
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pub struct Control {
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core1: Core1<Vec<u32>>,
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pub tx: sync_channel::Sender<usize>,
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pub rx: sync_channel::Receiver<usize>,
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}
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impl Control {
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pub fn start(stack_size: usize) -> Self {
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let stack = vec![0; stack_size / 4];
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let core1 = Core1::start(stack);
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let (core0_tx, core1_rx) = sync_channel(4);
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let (core1_tx, core0_rx) = sync_channel(4);
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*CHANNEL_0TO1.lock() = Some(core1_rx);
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*CHANNEL_1TO0.lock() = Some(core1_tx);
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Control {
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core1,
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tx: core0_tx,
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rx: core0_rx,
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}
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}
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pub fn reset(self) {
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*CHANNEL_0TO1.lock() = None;
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*CHANNEL_1TO0.lock() = None;
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self.core1.reset();
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}
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}
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pub static mut KERNEL_BUFFER: [u8; 16384] = [0; 16384];
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pub fn main(mut sc_tx: sync_channel::Sender<usize>, mut sc_rx: sync_channel::Receiver<usize>) {
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for i in sc_rx {
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sc_tx.send(*i * *i);
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#[no_mangle]
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pub fn main_core1() {
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println!("Core1 started");
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let mut core1_tx = None;
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while core1_tx.is_none() {
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core1_tx = CHANNEL_1TO0.lock().take();
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}
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let mut core1_tx = core1_tx.unwrap();
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let mut core1_rx = None;
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while core1_rx.is_none() {
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core1_rx = CHANNEL_0TO1.lock().take();
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}
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let core1_rx = core1_rx.unwrap();
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for i in core1_rx {
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core1_tx.send(*i * *i);
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}
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loop {}
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loop {}
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}
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@ -9,14 +9,12 @@ use libboard_zynq::{
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println,
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self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
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};
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use libsupport_zynq::{ram, boot};
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use libcortex_a9::{mutex::Mutex, sync_channel::{self, sync_channel}};
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use libsupport_zynq::ram;
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mod comms;
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mod pl;
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mod rtio;
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mod kernel;
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mod control;
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fn identifier_read(buf: &mut [u8]) -> &str {
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@ -32,10 +30,6 @@ fn identifier_read(buf: &mut [u8]) -> &str {
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}
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}
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static mut STACK_CORE1: [u32; 512] = [0; 512];
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static CHANNEL_0TO1: Mutex<Option<sync_channel::Receiver<usize>>> = Mutex::new(None);
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static CHANNEL_1TO0: Mutex<Option<sync_channel::Sender<usize>>> = Mutex::new(None);
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#[no_mangle]
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pub fn main_core0() {
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println!("ARTIQ runtime starting...");
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@ -53,22 +47,3 @@ pub fn main_core0() {
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comms::main();
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}
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#[no_mangle]
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pub fn main_core1() {
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println!("Core1 started");
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let mut core1_tx = None;
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while core1_tx.is_none() {
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core1_tx = CHANNEL_1TO0.lock().take();
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}
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let mut core1_tx = core1_tx.unwrap();
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let mut core1_rx = None;
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while core1_rx.is_none() {
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core1_rx = CHANNEL_0TO1.lock().take();
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}
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let mut core1_rx = core1_rx.unwrap();
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kernel::main(core1_tx, core1_rx);
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}
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