forked from M-Labs/artiq-zynq
zc706: add RTIO log channels
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parent
04e7690c03
commit
523524c319
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@ -113,6 +113,10 @@ class Simple(ZC706):
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phy = ttl_simple.Output(platform.request("user_led", i))
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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self.add_rtio(rtio_channels)
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@ -173,6 +177,9 @@ class NIST_CLOCK(ZC706):
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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self.add_rtio(rtio_channels)
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@ -220,6 +227,9 @@ class NIST_QC2(ZC706):
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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self.add_rtio(rtio_channels)
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