forked from M-Labs/artiq-zynq
Support for DRTIO 100MHz (#155)
Co-authored-by: mwojcik <mw@m-labs.hk> Co-committed-by: mwojcik <mw@m-labs.hk>
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@ -8,7 +8,10 @@ let
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vivado = import <artiq-fast/vivado.nix> { inherit pkgs; };
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# FSBL configuration supplied by Vivado 2020.1 for these boards:
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fsblTargets = ["zc702" "zc706" "zed"];
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sat_variants = ["satellite" "nist_clock_satellite" "nist_qc2_satellite" "acpki_nist_clock_satellite" "acpki_nist_qc2_satellite"];
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sat_variants = [
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"nist_clock_satellite" "nist_qc2_satellite" "acpki_nist_clock_satellite" "acpki_nist_qc2_satellite"
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"nist_clock_satellite_100mhz" "nist_qc2_satellite_100mhz" "acpki_nist_clock_satellite_100mhz" "acpki_nist_qc2_satellite_100mhz"
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];
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build = { target, variant, json ? null }: let
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szl = (import zynq-rs)."${target}-szl";
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fsbl = import "${zynq-rs}/nix/fsbl.nix" {
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@ -136,15 +139,19 @@ in
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(build { target = "zc706"; variant = "nist_clock"; }) //
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(build { target = "zc706"; variant = "nist_clock_master"; }) //
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(build { target = "zc706"; variant = "nist_clock_satellite"; }) //
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(build { target = "zc706"; variant = "nist_clock_satellite_100mhz"; }) //
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(build { target = "zc706"; variant = "nist_qc2"; }) //
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(build { target = "zc706"; variant = "nist_qc2_master"; }) //
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(build { target = "zc706"; variant = "nist_qc2_satellite"; }) //
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(build { target = "zc706"; variant = "nist_qc2_satellite_100mhz"; }) //
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(build { target = "zc706"; variant = "acpki_nist_clock"; }) //
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(build { target = "zc706"; variant = "acpki_nist_clock_master"; }) //
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(build { target = "zc706"; variant = "acpki_nist_clock_satellite"; }) //
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(build { target = "zc706"; variant = "acpki_nist_clock_satellite_100mhz"; }) //
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(build { target = "zc706"; variant = "acpki_nist_qc2"; }) //
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(build { target = "zc706"; variant = "acpki_nist_qc2_master"; }) //
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(build { target = "zc706"; variant = "acpki_nist_qc2_satellite"; }) //
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(build { target = "zc706"; variant = "acpki_nist_qc2_satellite_100mhz"; }) //
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(build { target = "kasli_soc"; variant = "demo"; json = ./demo.json; }) //
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(build { target = "kasli_soc"; variant = "master"; json = ./kasli-soc-master.json; }) //
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(build { target = "kasli_soc"; variant = "satellite"; json = ./kasli-soc-satellite.json; }) //
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@ -180,7 +180,7 @@ class GenericStandalone(SoCCore):
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class GenericMaster(SoCCore):
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def __init__(self, description, acpki=False):
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sys_clk_freq = 125e6
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rtio_clk_freq = 125e6
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rtio_clk_freq = description["rtio_frequency"]
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self.acpki = acpki
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self.rustc_cfg = dict()
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@ -300,7 +300,7 @@ class GenericMaster(SoCCore):
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class GenericSatellite(SoCCore):
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def __init__(self, description, acpki=False):
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sys_clk_freq = 125e6
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rtio_clk_freq = 125e6
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rtio_clk_freq = description["rtio_frequency"]
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self.acpki = acpki
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self.rustc_cfg = dict()
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@ -181,7 +181,7 @@ class ZC706(SoCCore):
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class _MasterBase(SoCCore):
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def __init__(self, acpki=False):
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def __init__(self, acpki=False, drtio100mhz=False):
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self.acpki = acpki
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self.rustc_cfg = dict()
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@ -195,6 +195,7 @@ class _MasterBase(SoCCore):
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platform.add_extension(si5324_fmc33)
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self.sys_clk_freq = 125e6
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rtio_clk_freq = 100e6 if drtio100mhz else self.sys_clk_freq
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platform = self.platform
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@ -208,7 +209,8 @@ class _MasterBase(SoCCore):
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("si5324_clkout"),
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pads=data_pads,
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sys_clk_freq=self.sys_clk_freq)
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sys_clk_freq=self.sys_clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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@ -247,7 +249,7 @@ class _MasterBase(SoCCore):
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.rustc_cfg["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
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self.rustc_cfg["rtio_frequency"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
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self.csr_devices.append("si5324_rst_n")
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@ -313,7 +315,7 @@ class _MasterBase(SoCCore):
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class _SatelliteBase(SoCCore):
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def __init__(self, acpki=False):
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def __init__(self, acpki=False, drtio100mhz=False):
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self.acpki = acpki
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self.rustc_cfg = dict()
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@ -327,6 +329,7 @@ class _SatelliteBase(SoCCore):
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platform.add_extension(si5324_fmc33)
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self.sys_clk_freq = 125e6
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rtio_clk_freq = 100e6 if drtio100mhz else self.sys_clk_freq
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platform = self.platform
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# SFP
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@ -342,7 +345,8 @@ class _SatelliteBase(SoCCore):
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("si5324_clkout"),
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pads=data_pads,
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sys_clk_freq=self.sys_clk_freq)
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sys_clk_freq=self.sys_clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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drtioaux_csr_group = []
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@ -595,37 +599,35 @@ class _NIST_QC2_RTIO:
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class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
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def __init__(self, acpki):
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def __init__(self, acpki, drtio100mhz):
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ZC706.__init__(self, acpki)
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_NIST_CLOCK_RTIO.__init__(self)
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class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO):
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def __init__(self, acpki):
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_MasterBase.__init__(self, acpki)
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def __init__(self, acpki, drtio100mhz):
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_MasterBase.__init__(self, acpki, drtio100mhz)
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_NIST_CLOCK_RTIO.__init__(self)
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class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO):
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def __init__(self, acpki):
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_SatelliteBase.__init__(self, acpki)
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def __init__(self, acpki, drtio100mhz):
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_SatelliteBase.__init__(self, acpki, drtio100mhz)
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_NIST_CLOCK_RTIO.__init__(self)
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class NIST_QC2(ZC706, _NIST_QC2_RTIO):
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def __init__(self, acpki):
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def __init__(self, acpki, drtio100mhz):
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ZC706.__init__(self, acpki)
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_NIST_QC2_RTIO.__init__(self)
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class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO):
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def __init__(self, acpki):
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_MasterBase.__init__(self, acpki)
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def __init__(self, acpki, drtio100mhz):
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_MasterBase.__init__(self, acpki, drtio100mhz)
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_NIST_QC2_RTIO.__init__(self)
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class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
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def __init__(self, acpki):
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_SatelliteBase.__init__(self, acpki)
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def __init__(self, acpki, drtio100mhz):
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_SatelliteBase.__init__(self, acpki, drtio100mhz)
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_NIST_QC2_RTIO.__init__(self)
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VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
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NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
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@ -663,7 +665,7 @@ def main():
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help="build gateware into the specified directory")
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parser.add_argument("-V", "--variant", default="nist_clock",
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help="variant: "
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"[acpki_]nist_clock/nist_qc2[_master/_satellite] "
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"[acpki_]nist_clock/nist_qc2[_master/_satellite][_100mhz]"
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"(default: %(default)s)")
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args = parser.parse_args()
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@ -671,12 +673,15 @@ def main():
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acpki = variant.startswith("acpki_")
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if acpki:
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variant = variant[6:]
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drtio100mhz = variant.endswith("_100mhz")
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if drtio100mhz:
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variant = variant[:-7]
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try:
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cls = VARIANTS[variant]
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except KeyError:
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raise SystemExit("Invalid variant (-V/--variant)")
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soc = cls(acpki=acpki)
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soc = cls(acpki=acpki, drtio100mhz=drtio100mhz)
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soc.finalize()
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if args.r is not None:
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@ -23,6 +23,7 @@ pub enum RtioClock {
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Ext0_Synth0_125to125,
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}
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#[allow(unreachable_code)]
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fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
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let mut res = RtioClock::Default;
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if let Ok(clk) = cfg.read_str("rtio_clock") {
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@ -46,8 +47,21 @@ fn get_rtio_clock_cfg(cfg: &Config) -> RtioClock {
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warn!("error reading configuration. Falling back to default.");
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}
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if res == RtioClock::Default {
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warn!("Using default configuration - internal 125MHz RTIO clock.");
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return RtioClock::Int_125;
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#[cfg(rtio_frequency="100.0")]
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{
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warn!("Using default configuration - internal 100MHz RTIO clock.");
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return RtioClock::Int_100;
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}
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#[cfg(rtio_frequency="125.0")]
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{
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warn!("Using default configuration - internal 125MHz RTIO clock.");
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return RtioClock::Int_125;
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}
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// anything else
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{
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warn!("Using default configuration - internal 125MHz RTIO clock.");
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return RtioClock::Int_125;
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}
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}
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res
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}
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@ -398,7 +398,7 @@ fn hardware_tick(ts: &mut u64, timer: &mut GlobalTimer) {
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}
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}
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#[cfg(has_si5324)]
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#[cfg(all(has_si5324, rtio_frequency = "125.0"))]
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 5,
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crystal_ref: true
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};
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#[cfg(all(has_si5324, rtio_frequency = "100.0"))]
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 5,
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nc1_ls : 10,
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n2_hs : 10,
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n2_ls : 250,
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n31 : 50,
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n32 : 50,
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bwsel : 4,
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crystal_ref: true
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};
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static mut LOG_BUFFER: [u8; 1<<17] = [0; 1<<17];
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#[no_mangle]
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