forked from M-Labs/artiq-zynq
add coraz7 + redpitaya targets
This commit is contained in:
parent
9259cffeb2
commit
113c8eb0b8
69
default.nix
69
default.nix
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@ -3,18 +3,24 @@ let
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pkgs = import <nixpkgs> { overlays = [ (import "${zynq-rs}/nix/mozilla-overlay.nix") ]; };
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rustPlatform = (import "${zynq-rs}/nix/rust-platform.nix" { inherit pkgs; });
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cargo-xbuild = (import zynq-rs).cargo-xbuild;
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zc706-szl = (import zynq-rs).zc706-szl;
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zc706-fsbl = import "${zynq-rs}/nix/fsbl.nix" { inherit pkgs; };
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mkbootimage = import "${zynq-rs}/nix/mkbootimage.nix" { inherit pkgs; };
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artiqpkgs = import <artiq-fast/default.nix> { inherit pkgs; };
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vivado = import <artiq-fast/vivado.nix> { inherit pkgs; };
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build-zc706 = { variant }: let
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# FSBL configuration supplied by Vivado 2020.1 for these boards:
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fsblTargets = ["zc702" "zc706" "zed"];
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build = { target, variant }: let
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szl = (import zynq-rs)."${target}-szl";
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fsbl = import "${zynq-rs}/nix/fsbl.nix" {
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inherit pkgs;
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board = target;
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};
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firmware = rustPlatform.buildRustPackage rec {
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# note: due to fetchCargoTarball, cargoSha256 depends on package name
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name = "zc706-firmware";
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name = "firmware";
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src = ./src;
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cargoSha256 = "1nibi7xhdx7qg0vi93n981fmc23flhvx67japn48kcmwsq3g46dm";
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cargoSha256 = "17313zy3vjna0pri4jpikcfbpydngxxpq48n3j5mwyw8d6jwhs3q";
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nativeBuildInputs = [
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pkgs.gnumake
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@ -26,7 +32,7 @@ let
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buildPhase = ''
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export XARGO_RUST_SRC="${rustPlatform.rust.rustc.src}/library"
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export CARGO_HOME=$(mktemp -d cargo-home.XXX)
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make VARIANT=${variant}
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make TARGET=${target} VARIANT=${variant}
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'';
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installPhase = ''
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@ -40,7 +46,7 @@ let
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doCheck = false;
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dontFixup = true;
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};
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gateware = pkgs.runCommand "zc706-${variant}-gateware"
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gateware = pkgs.runCommand "${target}-${variant}-gateware"
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{
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nativeBuildInputs = [
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(pkgs.python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq ])))
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@ -48,21 +54,21 @@ let
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];
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}
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''
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python ${./src/gateware}/zc706.py -g build -V ${variant}
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python ${./src/gateware}/${target}.py -g build -V ${variant}
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mkdir -p $out $out/nix-support
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cp build/top.bit $out
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echo file binary-dist $out/top.bit >> $out/nix-support/hydra-build-products
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'';
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# SZL startup
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jtag = pkgs.runCommand "zc706-${variant}-jtag" {}
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jtag = pkgs.runCommand "${target}-${variant}-jtag" {}
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''
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mkdir $out
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ln -s ${zc706-szl}/szl.elf $out
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ln -s ${szl}/szl.elf $out
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ln -s ${firmware}/runtime.bin $out
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ln -s ${gateware}/top.bit $out
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'';
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sd = pkgs.runCommand "zc706-${variant}-sd"
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sd = pkgs.runCommand "${target}-${variant}-sd"
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{
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buildInputs = [ mkbootimage ];
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}
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@ -71,7 +77,7 @@ let
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# can't write software (mkbootimage will segfault).
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bifdir=`mktemp -d`
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cd $bifdir
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ln -s ${zc706-szl}/szl.elf szl.elf
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ln -s ${szl}/szl.elf szl.elf
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ln -s ${firmware}/runtime.elf runtime.elf
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ln -s ${gateware}/top.bit top.bit
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cat > boot.bif << EOF
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@ -88,14 +94,14 @@ let
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'';
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# FSBL startup
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fsbl-sd = pkgs.runCommand "zc706-${variant}-fsbl-sd"
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fsbl-sd = pkgs.runCommand "${target}-${variant}-fsbl-sd"
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{
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buildInputs = [ mkbootimage ];
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}
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''
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bifdir=`mktemp -d`
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cd $bifdir
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ln -s ${zc706-fsbl}/fsbl.elf fsbl.elf
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ln -s ${fsbl}/fsbl.elf fsbl.elf
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ln -s ${gateware}/top.bit top.bit
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ln -s ${firmware}/runtime.elf runtime.elf
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cat > boot.bif << EOF
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@ -111,19 +117,30 @@ let
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echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
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'';
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in {
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"zc706-${variant}-firmware" = firmware;
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"zc706-${variant}-gateware" = gateware;
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"zc706-${variant}-jtag" = jtag;
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"zc706-${variant}-sd" = sd;
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"zc706-${variant}-fsbl-sd" = fsbl-sd;
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};
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"${target}-${variant}-firmware" = firmware;
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"${target}-${variant}-gateware" = gateware;
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"${target}-${variant}-jtag" = jtag;
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"${target}-${variant}-sd" = sd;
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} // (
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if builtins.elem target fsblTargets
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then {
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"${target}-${variant}-fsbl-sd" = fsbl-sd;
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}
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else {}
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);
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in
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(
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(build-zc706 { variant = "simple"; }) //
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(build-zc706 { variant = "nist_clock"; }) //
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(build-zc706 { variant = "nist_qc2"; }) //
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(build-zc706 { variant = "acpki_simple"; }) //
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(build-zc706 { variant = "acpki_nist_clock"; }) //
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(build-zc706 { variant = "acpki_nist_qc2"; }) //
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(build { target = "zc706"; variant = "simple"; }) //
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(build { target = "zc706"; variant = "nist_clock"; }) //
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(build { target = "zc706"; variant = "nist_qc2"; }) //
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(build { target = "zc706"; variant = "acpki_simple"; }) //
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(build { target = "zc706"; variant = "acpki_nist_clock"; }) //
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(build { target = "zc706"; variant = "acpki_nist_qc2"; }) //
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(build { target = "coraz7"; variant = "10"; }) //
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(build { target = "coraz7"; variant = "07s"; }) //
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(build { target = "coraz7"; variant = "acpki_10"; }) //
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(build { target = "coraz7"; variant = "acpki_07s"; }) //
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(build { target = "redpitaya"; variant = "simple"; }) //
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(build { target = "redpitaya"; variant = "acpki_simple"; }) //
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{ inherit zynq-rs; }
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)
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@ -37,9 +37,9 @@ checksum = "08c48aae112d48ed9f069b33538ea9e3e90aa263cfa3d1c24309612b1f7472de"
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[[package]]
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name = "cc"
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version = "1.0.61"
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version = "1.0.62"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "ed67cbde08356238e75fc4656be4749481eeffb09e19f320a25237d5221c985d"
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checksum = "f1770ced377336a88a67c473594ccc14eca6f4559217c34f64aac8f83d641b40"
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[[package]]
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name = "cfg-if"
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@ -56,7 +56,7 @@ checksum = "e3fcd8aba10d17504c87ef12d4f62ef404c6a4703d16682a9eb5543e6cf24455"
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[[package]]
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name = "core_io"
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version = "0.1.20200410"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#d623913535906739c31dc9838cdf1db4b975fb46"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#cb50c8d61b9ffbb4c88b5f2e96fa9f4394266c43"
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dependencies = [
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"memchr",
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]
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@ -109,9 +109,9 @@ dependencies = [
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[[package]]
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name = "futures"
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version = "0.3.7"
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version = "0.3.8"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "95314d38584ffbfda215621d723e0a3906f032e03ae5551e650058dac83d4797"
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checksum = "9b3b0c040a1fe6529d30b3c5944b280c7f0dcb2930d2c3062bca967b602583d0"
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dependencies = [
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"futures-channel",
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"futures-core",
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@ -123,9 +123,9 @@ dependencies = [
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[[package]]
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name = "futures-channel"
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version = "0.3.7"
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version = "0.3.8"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "0448174b01148032eed37ac4aed28963aaaa8cfa93569a08e5b479bbc6c2c151"
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checksum = "4b7109687aa4e177ef6fe84553af6280ef2778bdb7783ba44c9dc3399110fe64"
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dependencies = [
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"futures-core",
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"futures-sink",
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@ -133,21 +133,21 @@ dependencies = [
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[[package]]
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name = "futures-core"
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version = "0.3.7"
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version = "0.3.8"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "18eaa56102984bed2c88ea39026cff3ce3b4c7f508ca970cedf2450ea10d4e46"
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checksum = "847ce131b72ffb13b6109a221da9ad97a64cbe48feb1028356b836b47b8f1748"
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[[package]]
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name = "futures-io"
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version = "0.3.7"
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version = "0.3.8"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "6e1798854a4727ff944a7b12aa999f58ce7aa81db80d2dfaaf2ba06f065ddd2b"
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checksum = "611834ce18aaa1bd13c4b374f5d653e1027cf99b6b502584ff8c9a64413b30bb"
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[[package]]
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name = "futures-macro"
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version = "0.3.7"
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version = "0.3.8"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "e36fccf3fc58563b4a14d265027c627c3b665d7fed489427e88e7cc929559efe"
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checksum = "77408a692f1f97bcc61dc001d752e00643408fbc922e4d634c655df50d595556"
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dependencies = [
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"proc-macro-hack",
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"proc-macro2",
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@ -157,21 +157,21 @@ dependencies = [
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[[package]]
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name = "futures-sink"
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version = "0.3.7"
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version = "0.3.8"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "0e3ca3f17d6e8804ae5d3df7a7d35b2b3a6fe89dac84b31872720fc3060a0b11"
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checksum = "f878195a49cee50e006b02b93cf7e0a95a38ac7b776b4c4d9cc1207cd20fcb3d"
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[[package]]
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name = "futures-task"
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version = "0.3.7"
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version = "0.3.8"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "96d502af37186c4fef99453df03e374683f8a1eec9dcc1e66b3b82dc8278ce3c"
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checksum = "7c554eb5bf48b2426c4771ab68c6b14468b6e76cc90996f528c3338d761a4d0d"
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[[package]]
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name = "futures-util"
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version = "0.3.7"
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version = "0.3.8"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "abcb44342f62e6f3e8ac427b8aa815f724fd705dfad060b18ac7866c15bb8e34"
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checksum = "d304cff4a7b99cfb7986f7d43fbe93d175e72e704a8860787cc95e9ffd85cbd2"
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dependencies = [
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"futures-core",
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"futures-macro",
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@ -186,7 +186,7 @@ dependencies = [
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[[package]]
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name = "libasync"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#d623913535906739c31dc9838cdf1db4b975fb46"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#cb50c8d61b9ffbb4c88b5f2e96fa9f4394266c43"
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dependencies = [
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"embedded-hal",
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"libcortex_a9",
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@ -198,7 +198,7 @@ dependencies = [
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[[package]]
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name = "libboard_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#d623913535906739c31dc9838cdf1db4b975fb46"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#cb50c8d61b9ffbb4c88b5f2e96fa9f4394266c43"
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dependencies = [
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"bit_field",
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"embedded-hal",
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@ -222,7 +222,7 @@ dependencies = [
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[[package]]
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name = "libconfig"
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version = "0.1.0"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#d623913535906739c31dc9838cdf1db4b975fb46"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#cb50c8d61b9ffbb4c88b5f2e96fa9f4394266c43"
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dependencies = [
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"core_io",
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"fatfs",
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@ -233,7 +233,7 @@ dependencies = [
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[[package]]
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name = "libcortex_a9"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#d623913535906739c31dc9838cdf1db4b975fb46"
|
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#cb50c8d61b9ffbb4c88b5f2e96fa9f4394266c43"
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dependencies = [
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"bit_field",
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"libregister",
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@ -249,7 +249,7 @@ checksum = "c7d73b3f436185384286bd8098d17ec07c9a7d2388a6599f824d8502b529702a"
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[[package]]
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name = "libregister"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#d623913535906739c31dc9838cdf1db4b975fb46"
|
||||
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#cb50c8d61b9ffbb4c88b5f2e96fa9f4394266c43"
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dependencies = [
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"bit_field",
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"vcell",
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@ -259,7 +259,7 @@ dependencies = [
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[[package]]
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name = "libsupport_zynq"
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version = "0.0.0"
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||||
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#d623913535906739c31dc9838cdf1db4b975fb46"
|
||||
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#cb50c8d61b9ffbb4c88b5f2e96fa9f4394266c43"
|
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dependencies = [
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"compiler_builtins",
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"libboard_zynq",
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|
|
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@ -1,3 +1,4 @@
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TARGET := zc706
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VARIANT := simple
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all: ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin
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@ -7,10 +8,14 @@ all: ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin
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../build/pl.rs ../build/rustc-cfg: gateware/*
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mkdir -p ../build
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python gateware/zc706.py -r ../build/pl.rs -c ../build/rustc-cfg -V $(VARIANT)
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python gateware/$(TARGET).py -r ../build/pl.rs -c ../build/rustc-cfg -V $(VARIANT)
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../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg $(shell find . -print)
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XBUILD_SYSROOT_PATH=`pwd`/../build/sysroot cargo xbuild --release -p runtime --target-dir ../build/firmware
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cd runtime && \
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XBUILD_SYSROOT_PATH=`pwd`/../../build/sysroot \
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cargo xbuild --release \
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--target-dir ../../build/firmware \
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--no-default-features --features=target_$(TARGET)
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../build/runtime.bin: ../build/firmware/armv7-none-eabihf/release/runtime
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llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin
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@ -0,0 +1,194 @@
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#!/usr/bin/env python
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import argparse
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from operator import itemgetter
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from migen import *
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from migen.build.generic_platform import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen_axi.integration.soc_core import SoCCore
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from migen_axi.platforms import coraz7
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from misoc.interconnect.csr import *
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from misoc.integration import cpu_interface
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
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import dma
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import analyzer
|
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import acpki
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|
||||
|
||||
class RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk):
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self.clock_sel = CSRStorage()
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||||
self.pll_reset = CSRStorage(reset=1)
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||||
self.pll_locked = CSRStatus()
|
||||
self.clock_domains.cd_rtio = ClockDomain()
|
||||
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
|
||||
|
||||
rtio_external_clk = Signal()
|
||||
# user_sma_clock = platform.request("user_sma_clock")
|
||||
# platform.add_period_constraint(user_sma_clock.p, 8.0)
|
||||
# self.specials += Instance("IBUFDS",
|
||||
# i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
|
||||
# o_O=rtio_external_clk)
|
||||
|
||||
pll_locked = Signal()
|
||||
rtio_clk = Signal()
|
||||
rtiox4_clk = Signal()
|
||||
self.specials += [
|
||||
Instance("PLLE2_ADV",
|
||||
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
|
||||
|
||||
p_REF_JITTER1=0.01,
|
||||
p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
|
||||
i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
|
||||
# Warning: CLKINSEL=0 means CLKIN2 is selected
|
||||
i_CLKINSEL=~self.clock_sel.storage,
|
||||
|
||||
# VCO @ 1GHz when using 125MHz input
|
||||
p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
|
||||
i_CLKFBIN=self.cd_rtio.clk,
|
||||
i_RST=self.pll_reset.storage,
|
||||
|
||||
o_CLKFBOUT=rtio_clk,
|
||||
|
||||
p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
|
||||
o_CLKOUT0=rtiox4_clk),
|
||||
Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
|
||||
Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
|
||||
AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
|
||||
MultiReg(pll_locked, self.pll_locked.status)
|
||||
]
|
||||
|
||||
|
||||
class CoraZ7(SoCCore):
|
||||
def __init__(self, device_variant="10", acpki=False):
|
||||
self.acpki = acpki
|
||||
self.rustc_cfg = dict()
|
||||
|
||||
platform = coraz7.Platform(device_variant=device_variant)
|
||||
platform.toolchain.bitstream_commands.extend([
|
||||
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
|
||||
])
|
||||
ident = self.__class__.__name__
|
||||
if self.acpki:
|
||||
ident = "acpki_" + ident
|
||||
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
|
||||
|
||||
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
|
||||
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
|
||||
|
||||
self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
|
||||
self.csr_devices.append("rtio_crg")
|
||||
self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
|
||||
self.platform.add_false_path_constraints(
|
||||
self.ps7.cd_sys.clk,
|
||||
self.rtio_crg.cd_rtio.clk)
|
||||
|
||||
def add_rtio(self, rtio_channels):
|
||||
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
|
||||
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
|
||||
self.csr_devices.append("rtio_core")
|
||||
|
||||
if self.acpki:
|
||||
self.rustc_cfg["ki_impl"] = "acp"
|
||||
self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
|
||||
bus=self.ps7.s_axi_acp,
|
||||
user=self.ps7.s_axi_acp_user,
|
||||
evento=self.ps7.event.o)
|
||||
self.csr_devices.append("rtio")
|
||||
else:
|
||||
self.rustc_cfg["ki_impl"] = "csr"
|
||||
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
|
||||
self.csr_devices.append("rtio")
|
||||
|
||||
self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
|
||||
self.csr_devices.append("rtio_dma")
|
||||
|
||||
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
||||
[self.rtio.cri, self.rtio_dma.cri],
|
||||
[self.rtio_core.cri])
|
||||
self.csr_devices.append("cri_con")
|
||||
|
||||
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
||||
self.csr_devices.append("rtio_moninj")
|
||||
|
||||
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
|
||||
self.ps7.s_axi_hp1)
|
||||
self.csr_devices.append("rtio_analyzer")
|
||||
|
||||
|
||||
class Simple(CoraZ7):
|
||||
def __init__(self, **kwargs):
|
||||
CoraZ7.__init__(self, **kwargs)
|
||||
|
||||
platform = self.platform
|
||||
|
||||
rtio_channels = []
|
||||
for i in range(2):
|
||||
phy = ttl_simple.Output(platform.request("user_led", i))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
|
||||
rtio_channels.append(rtio.LogChannel())
|
||||
|
||||
self.add_rtio(rtio_channels)
|
||||
|
||||
|
||||
VARIANTS = {cls.__name__.lower(): cls for cls in [Simple]}
|
||||
|
||||
|
||||
def write_csr_file(soc, filename):
|
||||
with open(filename, "w") as f:
|
||||
f.write(cpu_interface.get_csr_rust(
|
||||
soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
|
||||
|
||||
|
||||
def write_rustc_cfg_file(soc, filename):
|
||||
with open(filename, "w") as f:
|
||||
for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
|
||||
if v is None:
|
||||
f.write("{}\n".format(k))
|
||||
else:
|
||||
f.write("{}=\"{}\"\n".format(k, v))
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(
|
||||
description="ARTIQ port to the Cora Z7 Zynq development kit")
|
||||
parser.add_argument("-r", default=None,
|
||||
help="build Rust interface into the specified file")
|
||||
parser.add_argument("-c", default=None,
|
||||
help="build Rust compiler configuration into the specified file")
|
||||
parser.add_argument("-g", default=None,
|
||||
help="build gateware into the specified directory")
|
||||
parser.add_argument("-V", "--variant", default="10",
|
||||
help="variant: "
|
||||
"[acpki_]10/07s "
|
||||
"(default: %(default)s)")
|
||||
args = parser.parse_args()
|
||||
|
||||
variant = args.variant.lower()
|
||||
acpki = variant.startswith("acpki_")
|
||||
if acpki:
|
||||
variant = variant[6:]
|
||||
try:
|
||||
soc = Simple(device_variant=variant, acpki=acpki)
|
||||
except KeyError:
|
||||
raise SystemExit("Invalid variant (-V/--variant)")
|
||||
soc.finalize()
|
||||
|
||||
if args.r is not None:
|
||||
write_csr_file(soc, args.r)
|
||||
if args.c is not None:
|
||||
write_rustc_cfg_file(soc, args.c)
|
||||
if args.g is not None:
|
||||
soc.build(build_dir=args.g)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -0,0 +1,191 @@
|
|||
#!/usr/bin/env python
|
||||
|
||||
import argparse
|
||||
from operator import itemgetter
|
||||
|
||||
from migen import *
|
||||
from migen.build.generic_platform import *
|
||||
from migen.genlib.resetsync import AsyncResetSynchronizer
|
||||
from migen.genlib.cdc import MultiReg
|
||||
from migen_axi.integration.soc_core import SoCCore
|
||||
from migen_axi.platforms import redpitaya
|
||||
from misoc.interconnect.csr import *
|
||||
from misoc.integration import cpu_interface
|
||||
|
||||
from artiq.gateware import rtio
|
||||
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
|
||||
|
||||
import dma
|
||||
import analyzer
|
||||
import acpki
|
||||
|
||||
|
||||
class RTIOCRG(Module, AutoCSR):
|
||||
def __init__(self, platform, rtio_internal_clk):
|
||||
self.clock_sel = CSRStorage()
|
||||
self.pll_reset = CSRStorage(reset=1)
|
||||
self.pll_locked = CSRStatus()
|
||||
self.clock_domains.cd_rtio = ClockDomain()
|
||||
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
|
||||
|
||||
rtio_external_clk = Signal()
|
||||
# user_sma_clock = platform.request("user_sma_clock")
|
||||
# platform.add_period_constraint(user_sma_clock.p, 8.0)
|
||||
# self.specials += Instance("IBUFDS",
|
||||
# i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
|
||||
# o_O=rtio_external_clk)
|
||||
|
||||
pll_locked = Signal()
|
||||
rtio_clk = Signal()
|
||||
rtiox4_clk = Signal()
|
||||
self.specials += [
|
||||
Instance("PLLE2_ADV",
|
||||
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
|
||||
|
||||
p_REF_JITTER1=0.01,
|
||||
p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
|
||||
i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
|
||||
# Warning: CLKINSEL=0 means CLKIN2 is selected
|
||||
i_CLKINSEL=~self.clock_sel.storage,
|
||||
|
||||
# VCO @ 1GHz when using 125MHz input
|
||||
p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
|
||||
i_CLKFBIN=self.cd_rtio.clk,
|
||||
i_RST=self.pll_reset.storage,
|
||||
|
||||
o_CLKFBOUT=rtio_clk,
|
||||
|
||||
p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
|
||||
o_CLKOUT0=rtiox4_clk),
|
||||
Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
|
||||
Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
|
||||
AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
|
||||
MultiReg(pll_locked, self.pll_locked.status)
|
||||
]
|
||||
|
||||
|
||||
class Redpitaya(SoCCore):
|
||||
def __init__(self, acpki=False):
|
||||
self.acpki = acpki
|
||||
self.rustc_cfg = dict()
|
||||
|
||||
platform = redpitaya.Platform()
|
||||
platform.toolchain.bitstream_commands.extend([
|
||||
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
|
||||
])
|
||||
ident = self.__class__.__name__
|
||||
if self.acpki:
|
||||
ident = "acpki_" + ident
|
||||
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
|
||||
|
||||
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
|
||||
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
|
||||
|
||||
self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
|
||||
self.csr_devices.append("rtio_crg")
|
||||
self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
|
||||
self.platform.add_false_path_constraints(
|
||||
self.ps7.cd_sys.clk,
|
||||
self.rtio_crg.cd_rtio.clk)
|
||||
|
||||
def add_rtio(self, rtio_channels):
|
||||
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
|
||||
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
|
||||
self.csr_devices.append("rtio_core")
|
||||
|
||||
if self.acpki:
|
||||
self.rustc_cfg["ki_impl"] = "acp"
|
||||
self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
|
||||
bus=self.ps7.s_axi_acp,
|
||||
user=self.ps7.s_axi_acp_user,
|
||||
evento=self.ps7.event.o)
|
||||
self.csr_devices.append("rtio")
|
||||
else:
|
||||
self.rustc_cfg["ki_impl"] = "csr"
|
||||
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
|
||||
self.csr_devices.append("rtio")
|
||||
|
||||
self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
|
||||
self.csr_devices.append("rtio_dma")
|
||||
|
||||
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
||||
[self.rtio.cri, self.rtio_dma.cri],
|
||||
[self.rtio_core.cri])
|
||||
self.csr_devices.append("cri_con")
|
||||
|
||||
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
||||
self.csr_devices.append("rtio_moninj")
|
||||
|
||||
self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
|
||||
self.ps7.s_axi_hp1)
|
||||
self.csr_devices.append("rtio_analyzer")
|
||||
|
||||
|
||||
class Simple(Redpitaya):
|
||||
def __init__(self, **kwargs):
|
||||
Redpitaya.__init__(self, **kwargs)
|
||||
|
||||
platform = self.platform
|
||||
|
||||
rtio_channels = []
|
||||
for i in range(2):
|
||||
phy = ttl_simple.Output(platform.request("user_led", i))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
|
||||
rtio_channels.append(rtio.LogChannel())
|
||||
|
||||
self.add_rtio(rtio_channels)
|
||||
|
||||
|
||||
VARIANTS = {cls.__name__.lower(): cls for cls in [Simple]}
|
||||
|
||||
|
||||
def write_csr_file(soc, filename):
|
||||
with open(filename, "w") as f:
|
||||
f.write(cpu_interface.get_csr_rust(
|
||||
soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
|
||||
|
||||
|
||||
def write_rustc_cfg_file(soc, filename):
|
||||
with open(filename, "w") as f:
|
||||
for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
|
||||
if v is None:
|
||||
f.write("{}\n".format(k))
|
||||
else:
|
||||
f.write("{}=\"{}\"\n".format(k, v))
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(
|
||||
description="ARTIQ port to the Redpitaya Zynq development kit")
|
||||
parser.add_argument("-r", default=None,
|
||||
help="build Rust interface into the specified file")
|
||||
parser.add_argument("-c", default=None,
|
||||
help="build Rust compiler configuration into the specified file")
|
||||
parser.add_argument("-g", default=None,
|
||||
help="build gateware into the specified directory")
|
||||
parser.add_argument("-V", "--variant", default="10",
|
||||
help="variant: "
|
||||
"[acpki_]simple "
|
||||
"(default: %(default)s)")
|
||||
args = parser.parse_args()
|
||||
|
||||
variant = args.variant.lower()
|
||||
acpki = variant.startswith("acpki_")
|
||||
if acpki:
|
||||
variant = variant[6:]
|
||||
soc = Simple(acpki=acpki)
|
||||
soc.finalize()
|
||||
|
||||
if args.r is not None:
|
||||
write_csr_file(soc, args.r)
|
||||
if args.c is not None:
|
||||
write_rustc_cfg_file(soc, args.c)
|
||||
if args.g is not None:
|
||||
soc.build(build_dir=args.g)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -7,6 +7,8 @@ edition = "2018"
|
|||
|
||||
[features]
|
||||
target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"]
|
||||
target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7", "libconfig/target_coraz7"]
|
||||
target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya", "libconfig/target_redpitaya"]
|
||||
default = ["target_zc706"]
|
||||
|
||||
[dependencies]
|
||||
|
|
|
|||
|
|
@ -3,6 +3,6 @@ let
|
|||
in
|
||||
pkgs.fetchgit {
|
||||
url = "https://git.m-labs.hk/M-Labs/zynq-rs.git";
|
||||
rev = "d623913535906739c31dc9838cdf1db4b975fb46";
|
||||
sha256 = "1bbxv1pgqkz9x5awshqh02r0ha0zc6yjabr5iwfbci8dpc63msv1";
|
||||
rev = "cb50c8d61b9ffbb4c88b5f2e96fa9f4394266c43";
|
||||
sha256 = "1wp81fm689l5ghh2bzlanqx7g066166ki39mlzhly48xczky6np2";
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue