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analyzer: fix endianness issue

This commit is contained in:
Sebastien Bourdeauducq 2020-07-16 17:10:09 +08:00
parent 84630d66e3
commit 10a12245a3
1 changed files with 10 additions and 1 deletions
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11
src/gateware/analyzer.py
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@ -7,6 +7,15 @@ from migen_axi.interconnect import axi
from artiq.gateware.rtio.analyzer import message_len, MessageEncoder from artiq.gateware.rtio.analyzer import message_len, MessageEncoder
def convert_endianness(signal):
assert len(signal) % 8 == 0
nbytes = len(signal)//8
signal_bytes = []
for i in range(nbytes):
signal_bytes.append(signal[8*i:8*(i+1)])
return Cat(*reversed(signal_bytes))
class AXIDMAWriter(Module, AutoCSR): class AXIDMAWriter(Module, AutoCSR):
def __init__(self, membus, max_outstanding_requests): def __init__(self, membus, max_outstanding_requests):
aw = len(membus.aw.addr) aw = len(membus.aw.addr)
@ -55,7 +64,7 @@ class AXIDMAWriter(Module, AutoCSR):
membus.w.id.eq(0), membus.w.id.eq(0),
membus.w.valid.eq(self.sink.stb), membus.w.valid.eq(self.sink.stb),
self.sink.ack.eq(membus.w.ready), self.sink.ack.eq(membus.w.ready),
membus.w.data.eq(self.sink.data), membus.w.data.eq(convert_endianness(self.sink.data)),
membus.w.strb.eq(2**(dw//8)-1), membus.w.strb.eq(2**(dw//8)-1),
] ]
beat_count = Signal(max=burst_length) beat_count = Signal(max=burst_length)