forked from M-Labs/artiq-zynq
dma: remove unneeded import
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@ -1,5 +1,4 @@
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from migen import *
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from migen import *
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from migen.genlib.record import Record, layout_len
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from migen.genlib.fsm import FSM
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from migen.genlib.fsm import FSM
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from misoc.interconnect.csr import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from misoc.interconnect import stream
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