forked from M-Labs/artiq-zynq
analyzer: use 32-bit byte_count
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parent
36338ea3b2
commit
0c6db0d12c
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@ -19,7 +19,7 @@ class AXIDMAWriter(Module, AutoCSR):
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# All numbers in bytes
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# All numbers in bytes
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self.base_address = CSRStorage(aw, alignment_bits=alignment_bits)
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self.base_address = CSRStorage(aw, alignment_bits=alignment_bits)
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self.last_address = CSRStorage(aw, alignment_bits=alignment_bits)
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self.last_address = CSRStorage(aw, alignment_bits=alignment_bits)
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self.byte_count = CSRStatus(64) # only read when shut down
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self.byte_count = CSRStatus(32) # only read when shut down
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self.make_request = Signal()
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self.make_request = Signal()
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self.sink = stream.Endpoint([("data", dw)])
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self.sink = stream.Endpoint([("data", dw)])
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@ -71,7 +71,7 @@ class AXIDMAWriter(Module, AutoCSR):
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)
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)
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]
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]
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message_count = Signal(64 - log2_int(message_len//8))
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message_count = Signal(32 - log2_int(message_len//8))
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self.comb += self.byte_count.status.eq(
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self.comb += self.byte_count.status.eq(
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message_count << log2_int(message_len//8))
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message_count << log2_int(message_len//8))
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self.sync += [
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self.sync += [
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