134 lines
4.7 KiB
Diff
134 lines
4.7 KiB
Diff
diff --git a/software/glasgow/access/direct/demultiplexer.py b/software/glasgow/access/direct/demultiplexer.py
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index 3df8c2e..068b40e 100644
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--- a/software/glasgow/access/direct/demultiplexer.py
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+++ b/software/glasgow/access/direct/demultiplexer.py
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@@ -30,7 +30,7 @@ from .. import AccessDemultiplexer, AccessDemultiplexerInterface
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#
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# To deal with this, use requests of at most 1024 EP buffer sizes (512 KiB with the FX2) as
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# an arbitrary cutoff, and hope for the best.
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-_max_packets_per_ep = 1024
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+_max_packets_per_ep = 2048
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# USB has the limitation that all transactions are host-initiated. Therefore, if we do not queue
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# reads for the IN endpoints quickly enough, the HC will not even poll the device, and the buffer
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@@ -52,7 +52,7 @@ _max_packets_per_ep = 1024
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# To try and balance these effects, we choose a medium buffer size that should work well with most
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# applications. It's possible that this will need to become customizable later, but for now
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# a single fixed value works.
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-_packets_per_xfer = 32
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+_packets_per_xfer = 512
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# Queue as many transfers as we can, but no more than 10, as the returns beyond that point
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# are diminishing.
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diff --git a/software/glasgow/applet/all.py b/software/glasgow/applet/all.py
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index 35b8960..3f37b9f 100644
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--- a/software/glasgow/applet/all.py
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+++ b/software/glasgow/applet/all.py
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@@ -44,3 +44,5 @@ from .video.rgb_input import VideoRGBInputApplet
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from .video.vga_output import VGAOutputApplet
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from .video.vga_terminal import VGATerminalApplet
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from .video.ws2812_output import VideoWS2812OutputApplet
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+
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+from .logic import LogicApplet
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diff --git a/software/glasgow/applet/logic.py b/software/glasgow/applet/logic.py
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new file mode 100644
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index 0000000..483e99e
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--- /dev/null
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+++ b/software/glasgow/applet/logic.py
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@@ -0,0 +1,95 @@
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+import sys
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+import logging
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+import os
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+import asyncio
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+from nmigen.compat import *
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+from nmigen.compat.genlib.cdc import MultiReg
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+
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+from . import *
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+
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+
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+class LogicSubtarget(Module):
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+ def __init__(self, pads, in_fifo):
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+ input = Signal.like(pads.d_t.i)
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+ latch = Signal.like(pads.d_t.i)
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+ self.submodules += MultiReg(pads.d_t.i, input)
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+
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+ self.comb += [
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+ in_fifo.din[0:4].eq(input[0:4]),
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+ in_fifo.din[4:8].eq(latch[0:4]),
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+ ]
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+
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+ self.submodules.fsm = FSM()
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+ self.fsm.act("CAPTURE-1",
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+ NextValue(latch, input),
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+ NextState("CAPTURE-2")
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+ )
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+ self.fsm.act("CAPTURE-2",
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+ in_fifo.we.eq(1),
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+ If(in_fifo.writable,
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+ NextState("CAPTURE-1")
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+ ).Else(
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+ NextState("OVERFLOW")
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+ )
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+ )
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+ self.fsm.act("OVERFLOW",
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+ NextState("OVERFLOW")
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+ )
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+
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+
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+async def async_stdout(limit=asyncio.streams._DEFAULT_LIMIT, loop=None):
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+ if loop is None:
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+ loop = asyncio.get_event_loop()
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+
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+ writer_transport, writer_protocol = await loop.connect_write_pipe(
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+ lambda: asyncio.streams.FlowControlMixin(loop=loop),
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+ os.fdopen(sys.stdout.fileno(), "wb"))
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+ writer = asyncio.streams.StreamWriter(
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+ writer_transport, writer_protocol, None, loop)
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+
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+ return writer
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+
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+
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+class LogicApplet(GlasgowApplet, name="logic"):
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+ logger = logging.getLogger(__name__)
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+ preview = True
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+
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+ @classmethod
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+ def add_build_arguments(cls, parser, access):
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+ super().add_build_arguments(parser, access)
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+
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+ access.add_pin_set_argument(parser, "d", required=True, width=range(5))
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+
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+ def build(self, target, args):
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+ self.mux_interface = iface = target.multiplexer.claim_interface(self, args)
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+ iface.add_subtarget(LogicSubtarget(
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+ pads=iface.get_pads(args, pin_sets=("d",)),
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+ in_fifo=iface.get_in_fifo(auto_flush=False, depth=16384),
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+ ))
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+
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+ @classmethod
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+ def add_run_arguments(cls, parser, access):
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+ super().add_run_arguments(parser, access)
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+
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+ async def run(self, device, args):
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+ return await device.demultiplexer.claim_interface(self, self.mux_interface, args)
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+
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+ @classmethod
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+ def add_interact_arguments(cls, parser):
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+ pass
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+
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+ async def interact(self, device, args, iface):
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+ output_stream = await async_stdout()
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+ while True:
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+ data = await iface.read(65536)
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+ output_stream.write(data)
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+ if output_stream.is_closing():
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+ print("glasgow: stdout closed, terminating", file=sys.stderr)
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+ return
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+
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+# ------------------------------------------------------------------------------------------------
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+
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+class LogicAppletTestCase(GlasgowAppletTestCase, applet=LogicApplet):
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+ @synthesis_test
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+ def test_build(self):
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+ self.assertBuilds()
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