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3fc91befca
...
2822f7c01e
@ -1,8 +1,8 @@
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diff --git a/software/glasgow/applet/all.py b/software/glasgow/applet/all.py
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index 35b8960..3f37b9f 100644
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index 5aa86ea..715e5ec 100644
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--- a/software/glasgow/applet/all.py
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+++ b/software/glasgow/applet/all.py
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@@ -44,3 +44,5 @@ from .video.rgb_input import VideoRGBInputApplet
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@@ -43,3 +43,5 @@ from .video.rgb_input import VideoRGBInputApplet
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from .video.vga_output import VGAOutputApplet
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from .video.vga_terminal import VGATerminalApplet
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from .video.ws2812_output import VideoWS2812OutputApplet
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@ -10,45 +10,34 @@ index 35b8960..3f37b9f 100644
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+from .logic import LogicApplet
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diff --git a/software/glasgow/applet/logic.py b/software/glasgow/applet/logic.py
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new file mode 100644
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index 0000000..529d4e1
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index 0000000..eabca52
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--- /dev/null
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+++ b/software/glasgow/applet/logic.py
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@@ -0,0 +1,77 @@
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@@ -0,0 +1,66 @@
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+import sys
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+import logging
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+import asyncio
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+from nmigen.compat import *
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+from nmigen.compat.genlib.cdc import MultiReg
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+
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+from . import *
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+
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+
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+class LogicSubtarget(Module):
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+ def __init__(self, pads, in_fifo):
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+ input = Signal.like(pads.d_t.i)
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+ latch = Signal.like(pads.d_t.i)
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+ self.submodules += MultiReg(pads.d_t.i, input)
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+ latch = Signal(4)
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+
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+ self.comb += [
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+ in_fifo.din[0:4].eq(input[0:4]),
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+ in_fifo.din[4:8].eq(latch[0:4]),
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+ in_fifo.din.eq(Cat(pads.d_t.i[:4], latch)),
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+ ]
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+
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+ self.submodules.fsm = FSM()
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+ self.fsm.act("CAPTURE-1",
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+ NextValue(latch, input),
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+ NextValue(latch, pads.d_t.i),
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+ NextState("CAPTURE-2")
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+ )
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+ self.fsm.act("CAPTURE-2",
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+ in_fifo.we.eq(1),
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+ If(in_fifo.writable,
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+ NextState("CAPTURE-1")
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+ ).Else(
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+ NextState("OVERFLOW")
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+ )
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+ )
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+ self.fsm.act("OVERFLOW",
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+ NextState("OVERFLOW")
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+ )
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+
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+
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@ -66,7 +55,7 @@ index 0000000..529d4e1
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+ self.mux_interface = iface = target.multiplexer.claim_interface(self, args)
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+ iface.add_subtarget(LogicSubtarget(
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+ pads=iface.get_pads(args, pin_sets=("d",)),
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+ in_fifo=iface.get_in_fifo(auto_flush=False, depth=8192),
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+ in_fifo=iface.get_in_fifo(auto_flush=False),
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+ ))
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+
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+ @classmethod
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@ -85,7 +74,7 @@ index 0000000..529d4e1
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+ data = await iface.read(65536)
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+ sys.stdout.buffer.write(data)
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+
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+# ------------------------------------------------------------------------------------------------
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+# -------------------------------------------------------------------------------------------------
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+
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+class LogicAppletTestCase(GlasgowAppletTestCase, applet=LogicApplet):
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+ @synthesis_test
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@ -11,7 +11,7 @@ fp = os.fdopen(sys.stdout.fileno(), "wb")
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while True:
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sample = 0
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for _ in range(2):
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sample <<= 4
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sample <<= 2
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ref_phase = (ref_phase + ref_ftw) & 0xffffffff
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delta = 0
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@ -23,7 +23,7 @@ struct Config {
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refpll_kp: i64
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}
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fn read_config_from_file<P: AsRef<Path>>(path: P) -> Result<Config, Box<dyn Error>> {
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fn read_config_from_file<P: AsRef<Path>>(path: P) -> Result<Config, Box<Error>> {
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let file = File::open(path)?;
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let reader = BufReader::new(file);
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let u = serde_json::from_reader(reader)?;
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@ -114,8 +114,8 @@ pub fn sample(command: &str, mut callback: impl FnMut(u8, u8)) {
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let mut last_sample = 0;
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loop {
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reader.read_exact(&mut buffer).unwrap();
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for shift in [4u8, 0u8].iter() {
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let sample = (buffer[0] >> shift) & 0x0f;
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for shift in [2u8, 0u8].iter() {
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let sample = (buffer[0] >> shift) & 0x03;
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let rising = sample & !last_sample;
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let falling = !sample & last_sample;
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callback(rising, falling);
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