From e9a5132de5dd1770d2198b0d68bee390f973278f Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 3 Oct 2019 19:45:50 +0800
Subject: [PATCH] simulate.py: consistent output format

---
 simulate.py | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/simulate.py b/simulate.py
index 5929ac6..64ca374 100644
--- a/simulate.py
+++ b/simulate.py
@@ -1,8 +1,7 @@
 import sys, os
 
-sample_rate = 24e6
-ref_frequency = 2.0e6
-
+sample_rate = 48e6
+ref_frequency = 1.97e6
 
 ref_phase = 0
 ref_ftw = int(ref_frequency*2**32/sample_rate)
@@ -10,9 +9,16 @@ ref_ftw = int(ref_frequency*2**32/sample_rate)
 fp = os.fdopen(sys.stdout.fileno(), "wb")
 
 while True:
-    ref_phase = (ref_phase + ref_ftw) & 0xffffffff
-
     sample = 0
-    if ref_phase >= 0x80000000:
-        sample |= 0x01
+    for _ in range(2):
+        sample <<= 4
+
+        ref_phase = (ref_phase + ref_ftw) & 0xffffffff
+        delta = 0
+        meas_phase = (ref_phase + delta) & 0xffffffff
+
+        if ref_phase >= 0x80000000:
+            sample |= 0x01
+        if meas_phase >= 0x80000000:
+            sample |= 0x02
     fp.write(bytes([sample]))