move to glasgow (faster sample rate and no USB bug)
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@ -1,6 +1,6 @@
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{
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{
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"sample_command": "sudo sigrok-cli -O binary -d fx2lafw --config samplerate=6000000 --continuous",
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"sample_command": "glasgow run logic -V 3.3 --pins-d 0,1",
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"sample_rate": 6e6,
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"sample_rate": 48e6,
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"freq_min": 1.9e6,
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"freq_min": 1.9e6,
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"freq_max": 2.1e6,
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"freq_max": 2.1e6,
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"bit_ref": 0,
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"bit_ref": 0,
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82
glasgow-applet.diff
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82
glasgow-applet.diff
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@ -0,0 +1,82 @@
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diff --git a/software/glasgow/applet/all.py b/software/glasgow/applet/all.py
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index 5aa86ea..715e5ec 100644
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--- a/software/glasgow/applet/all.py
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+++ b/software/glasgow/applet/all.py
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@@ -43,3 +43,5 @@ from .video.rgb_input import VideoRGBInputApplet
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from .video.vga_output import VGAOutputApplet
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from .video.vga_terminal import VGATerminalApplet
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from .video.ws2812_output import VideoWS2812OutputApplet
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+
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+from .logic import LogicApplet
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diff --git a/software/glasgow/applet/logic.py b/software/glasgow/applet/logic.py
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new file mode 100644
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index 0000000..eabca52
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--- /dev/null
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+++ b/software/glasgow/applet/logic.py
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@@ -0,0 +1,66 @@
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+import sys
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+import logging
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+import asyncio
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+from nmigen.compat import *
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+
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+from . import *
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+
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+
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+class LogicSubtarget(Module):
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+ def __init__(self, pads, in_fifo):
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+ latch = Signal(4)
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+
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+ self.comb += [
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+ in_fifo.din.eq(Cat(pads.d_t.i[:4], latch)),
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+ ]
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+
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+ self.submodules.fsm = FSM()
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+ self.fsm.act("CAPTURE-1",
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+ NextValue(latch, pads.d_t.i),
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+ NextState("CAPTURE-2")
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+ )
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+ self.fsm.act("CAPTURE-2",
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+ in_fifo.we.eq(1),
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+ NextState("CAPTURE-1")
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+ )
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+
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+
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+class LogicApplet(GlasgowApplet, name="logic"):
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+ logger = logging.getLogger(__name__)
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+ preview = True
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+
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+ @classmethod
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+ def add_build_arguments(cls, parser, access):
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+ super().add_build_arguments(parser, access)
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+
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+ access.add_pin_set_argument(parser, "d", required=True, width=range(5))
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+
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+ def build(self, target, args):
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+ self.mux_interface = iface = target.multiplexer.claim_interface(self, args)
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+ iface.add_subtarget(LogicSubtarget(
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+ pads=iface.get_pads(args, pin_sets=("d",)),
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+ in_fifo=iface.get_in_fifo(auto_flush=False),
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+ ))
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+
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+ @classmethod
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+ def add_run_arguments(cls, parser, access):
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+ super().add_run_arguments(parser, access)
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+
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+ async def run(self, device, args):
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+ return await device.demultiplexer.claim_interface(self, self.mux_interface, args)
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+
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+ @classmethod
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+ def add_interact_arguments(cls, parser):
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+ pass
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+
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+ async def interact(self, device, args, iface):
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+ while True:
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+ data = await iface.read(65536)
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+ sys.stdout.buffer.write(data)
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+
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+# -------------------------------------------------------------------------------------------------
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+
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+class LogicAppletTestCase(GlasgowAppletTestCase, applet=LogicApplet):
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+ @synthesis_test
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+ def test_build(self):
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+ self.assertBuilds()
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@ -110,14 +110,16 @@ pub fn sample(command: &str, mut callback: impl FnMut(u8, u8)) {
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.spawn()
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.spawn()
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.unwrap();
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.unwrap();
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let mut reader = BufReader::new(child.stdout.unwrap());
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let mut reader = BufReader::new(child.stdout.unwrap());
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let mut br_sample = [0; 1];
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let mut buffer = [0; 1];
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let mut last_sample = 0;
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let mut last_sample = 0;
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loop {
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loop {
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reader.read_exact(&mut br_sample).unwrap();
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reader.read_exact(&mut buffer).unwrap();
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let sample = br_sample[0];
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for shift in [4u8, 0u8].iter() {
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let sample = (buffer[0] >> shift) & 0x0f;
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let rising = sample & !last_sample;
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let rising = sample & !last_sample;
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let falling = !sample & last_sample;
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let falling = !sample & last_sample;
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callback(rising, falling);
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callback(rising, falling);
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last_sample = sample;
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last_sample = sample;
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}
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}
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}
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}
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}
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