From 0bb9fc90f052242c0d691befcaa466843df0a6cc Mon Sep 17 00:00:00 2001
From: Ryan Summers <ryan.summers@vertigo-designs.com>
Date: Mon, 31 May 2021 17:42:01 +0200
Subject: [PATCH] Simplifying loop logic

---
 src/iface/interface.rs | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/iface/interface.rs b/src/iface/interface.rs
index 05dae4e..f32f796 100644
--- a/src/iface/interface.rs
+++ b/src/iface/interface.rs
@@ -594,12 +594,8 @@ impl<'a, DeviceT> Interface<'a, DeviceT>
 
     fn socket_ingress(&mut self, sockets: &mut SocketSet, timestamp: Instant) -> bool {
         let mut processed_any = false;
-        loop {
-            let &mut Self { ref mut device, ref mut inner } = self;
-            let (rx_token, tx_token) = match device.receive() {
-                None => break,
-                Some(tokens) => tokens,
-            };
+        let &mut Self { ref mut device, ref mut inner } = self;
+        while let Some((rx_token, tx_token)) = device.receive() {
             match rx_token.consume(timestamp, |frame| {
                 match inner.device_capabilities.medium {
                     #[cfg(feature = "medium-ethernet")]
@@ -645,6 +641,7 @@ impl<'a, DeviceT> Interface<'a, DeviceT>
                 Ok(_) => {},
             };
         }
+
         processed_any
     }