161 lines
5.1 KiB
Rust
161 lines
5.1 KiB
Rust
#![no_std]
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#![no_main]
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extern crate panic_itm;
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use cortex_m::{iprintln, iprint};
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use embedded_hal::{
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digital::v2::OutputPin,
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blocking::delay::DelayMs
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};
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use stm32f4xx_hal::{
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rcc::RccExt,
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gpio::GpioExt,
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time::U32Ext,
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stm32::ITM,
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delay::Delay,
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spi::Spi,
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time::Hertz
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};
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use enc424j600;
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use enc424j600::EthController;
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///
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use stm32f4xx_hal::{
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stm32::SPI1,
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gpio::{
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gpioa::{PA5, PA6, PA7, PA4},
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Alternate, AF5, Output, PushPull
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},
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};
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type BoosterSpiEth = enc424j600::SpiEth<
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Spi<SPI1, (PA5<Alternate<AF5>>, PA6<Alternate<AF5>>, PA7<Alternate<AF5>>)>,
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PA4<Output<PushPull>>>;
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#[rtic::app(device = stm32f4xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
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const APP: () = {
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struct Resources {
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spi_eth: BoosterSpiEth,
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delay: Delay,
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itm: ITM,
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}
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#[init()]
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fn init(mut c: init::Context) -> init::LateResources {
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c.core.SCB.enable_icache();
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c.core.SCB.enable_dcache(&mut c.core.CPUID);
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let clocks = c.device.RCC.constrain()
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.cfgr
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.sysclk(168.mhz())
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.hclk(168.mhz())
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//.pclk1(32.mhz())
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.pclk1(42.mhz())
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//.pclk2(64.mhz())
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.require_pll48clk()
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.freeze();
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let mut delay = Delay::new(c.core.SYST, clocks);
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// Init ITM
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let mut itm = c.core.ITM;
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let stim0 = &mut itm.stim[0];
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iprintln!(stim0,
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"Eth TX Pinging on STM32-F407 via NIC100/ENC424J600");
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// NIC100 / ENC424J600 Set-up
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let spi1 = c.device.SPI1;
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let gpioa = c.device.GPIOA.split();
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// Mapping: see Table 9, STM32F407ZG Manual
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let spi1_sck = gpioa.pa5.into_alternate_af5();
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let spi1_miso = gpioa.pa6.into_alternate_af5();
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let spi1_mosi = gpioa.pa7.into_alternate_af5();
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let spi1_nss = gpioa.pa4.into_push_pull_output();
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// Map SPISEL: see Table 1, NIC100 Manual
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let mut spisel = gpioa.pa1.into_push_pull_output();
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spisel.set_high().unwrap();
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delay.delay_ms(1_u32);
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spisel.set_low().unwrap();
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// Create SPI1 for HAL
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let mut spi_eth = {
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let spi_eth_port = Spi::spi1(
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spi1, (spi1_sck, spi1_miso, spi1_mosi),
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enc424j600::spi::interfaces::SPI_MODE,
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Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ),
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clocks);
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enc424j600::SpiEth::new(spi_eth_port, spi1_nss)
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};
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// Init
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match spi_eth.init_dev(&mut delay) {
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Ok(_) => {
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iprintln!(stim0, "Initializing Ethernet...")
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}
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Err(_) => {
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panic!("Ethernet initialization failed!")
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}
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}
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// Read MAC
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let mut eth_mac_addr: [u8; 6] = [0; 6];
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spi_eth.read_from_mac(&mut eth_mac_addr);
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for i in 0..6 {
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let byte = eth_mac_addr[i];
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match i {
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0 => iprint!(stim0, "MAC Address = {:02x}-", byte),
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1..=4 => iprint!(stim0, "{:02x}-", byte),
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5 => iprint!(stim0, "{:02x}\n", byte),
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_ => ()
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};
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}
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// Init Rx/Tx buffers
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spi_eth.init_rxbuf();
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spi_eth.init_txbuf();
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iprintln!(stim0, "Ethernet controller initialized");
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init::LateResources {
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spi_eth,
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delay,
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itm,
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}
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}
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#[idle(resources=[spi_eth, delay, itm])]
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fn idle(c: idle::Context) -> ! {
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let stim0 = &mut c.resources.itm.stim[0];
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// Testing Eth TX
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let eth_tx_dat: [u8; 64] = [
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x08, 0x60,
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0x6e, 0x44, 0x42, 0x95, 0x08, 0x06, 0x00, 0x01,
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0x08, 0x00, 0x06, 0x04, 0x00, 0x01, 0x08, 0x60,
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0x6e, 0x44, 0x42, 0x95, 0xc0, 0xa8, 0x01, 0x64,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xa8,
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0x01, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x69, 0xd0, 0x85, 0x9f
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];
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loop {
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let mut eth_tx_packet = enc424j600::tx::TxPacket::new();
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eth_tx_packet.update_frame(ð_tx_dat, 64);
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iprint!(stim0,
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"Sending packet (len={:}): ", eth_tx_packet.get_frame_length());
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for i in 0..20 {
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let byte = eth_tx_packet.get_frame_byte(i);
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match i {
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0 => iprint!(stim0, "dest={:02x}-", byte),
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6 => iprint!(stim0, "src={:02x}-", byte),
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12 => iprint!(stim0, "data={:02x}", byte),
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1..=4 | 7..=10 => iprint!(stim0, "{:02x}-", byte),
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13..=14 | 16..=18 => iprint!(stim0, "{:02x}", byte),
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5 | 11 | 15 => iprint!(stim0, "{:02x} ", byte),
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19 => iprint!(stim0, "{:02x} ...\n", byte),
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_ => ()
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};
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}
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c.resources.spi_eth.send_raw_packet(ð_tx_packet);
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iprintln!(stim0, "Packet sent");
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c.resources.delay.delay_ms(100_u32);
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}
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}
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};
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