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ENC424J600
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Remove cortex-m dependencies for delay #2

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sb10q merged 8 commits from occheung/ENC424J600:generalize_delay into master 2021-01-25 12:35:23 +08:00
Conversation 11 Commits 8 Files Changed 4 +12 -12
4 changed files with 12 additions and 12 deletions
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Showing only changes of commit d557e2542d - Show all commits

6
examples/tcp_stm32f407.rs
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@ -180,7 +180,7 @@ const APP: () = {
// Read MAC // Read MAC
let mut eth_mac_addr: [u8; 6] = [0; 6]; let mut eth_mac_addr: [u8; 6] = [0; 6];
spi_eth.read_from_mac(&mut eth_mac_addr).unwrap(); spi_eth.read_from_mac(&mut eth_mac_addr);
sb10q commented 2021-01-22 18:01:48 +08:00
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unrelated change

unrelated change
for i in 0..6 { for i in 0..6 {
let byte = eth_mac_addr[i]; let byte = eth_mac_addr[i];
match i { match i {
@ -192,8 +192,8 @@ const APP: () = {
} }
// Init Rx/Tx buffers // Init Rx/Tx buffers
spi_eth.init_rxbuf().unwrap(); spi_eth.init_rxbuf();
spi_eth.init_txbuf().unwrap(); spi_eth.init_txbuf();
iprintln!(stim0, "Ethernet controller initialized"); iprintln!(stim0, "Ethernet controller initialized");
// Init smoltcp interface // Init smoltcp interface

8
examples/tx_stm32f407.rs
View File

@ -102,7 +102,7 @@ const APP: () = {
// Read MAC // Read MAC
let mut eth_mac_addr: [u8; 6] = [0; 6]; let mut eth_mac_addr: [u8; 6] = [0; 6];
spi_eth.read_from_mac(&mut eth_mac_addr).unwrap(); spi_eth.read_from_mac(&mut eth_mac_addr);
for i in 0..6 { for i in 0..6 {
let byte = eth_mac_addr[i]; let byte = eth_mac_addr[i];
match i { match i {
@ -114,8 +114,8 @@ const APP: () = {
} }
// Init Rx/Tx buffers // Init Rx/Tx buffers
spi_eth.init_rxbuf().unwrap(); spi_eth.init_rxbuf();
spi_eth.init_txbuf().unwrap(); spi_eth.init_txbuf();
iprintln!(stim0, "Ethernet controller initialized"); iprintln!(stim0, "Ethernet controller initialized");
init::LateResources { init::LateResources {
@ -157,7 +157,7 @@ const APP: () = {
_ => () _ => ()
}; };
} }
c.resources.spi_eth.send_raw_packet(&eth_tx_packet).unwrap(); c.resources.spi_eth.send_raw_packet(&eth_tx_packet);
iprintln!(stim0, "Packet sent"); iprintln!(stim0, "Packet sent");
c.resources.delay.delay_ms(100_u32); c.resources.delay.delay_ms(100_u32);
} }

4
src/lib.rs
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@ -54,9 +54,9 @@ pub struct SpiEth<SPI: Transfer<u8>,
impl <SPI: Transfer<u8>, impl <SPI: Transfer<u8>,
NSS: OutputPin, NSS: OutputPin,
F: FnMut(u32) -> ()> SpiEth<SPI, NSS, F> { F: FnMut(u32) -> ()> SpiEth<SPI, NSS, F> {
pub fn new(spi: SPI, nss: NSS, f: F) -> Self { pub fn new(spi: SPI, nss: NSS, delay_ns: F) -> Self {
SpiEth { SpiEth {
spi_port: spi::SpiPort::new(spi, nss, f), spi_port: spi::SpiPort::new(spi, nss, delay_ns),
rx_buf: rx::RxBuffer::new(), rx_buf: rx::RxBuffer::new(),
tx_buf: tx::TxBuffer::new() tx_buf: tx::TxBuffer::new()
} }

6
src/spi.rs
View File

@ -1,5 +1,5 @@
use embedded_hal::{ use embedded_hal::{
blocking::{spi::Transfer}, blocking::spi::Transfer,
sb10q commented 2021-01-22 18:02:29 +08:00
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not needed

not needed
digital::v2::OutputPin, digital::v2::OutputPin,
}; };
@ -68,13 +68,13 @@ impl <SPI: Transfer<u8>,
NSS: OutputPin, NSS: OutputPin,
F: FnMut(u32) -> ()> SpiPort<SPI, NSS, F> { F: FnMut(u32) -> ()> SpiPort<SPI, NSS, F> {
// TODO: return as Result() // TODO: return as Result()
pub fn new(spi: SPI, mut nss: NSS, f: F) -> Self { pub fn new(spi: SPI, mut nss: NSS, delay_ns: F) -> Self {
sb10q commented 2021-01-22 18:03:04 +08:00
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why f and not delay_ns?

why ``f`` and not ``delay_ns``?
nss.set_high(); nss.set_high();
SpiPort { SpiPort {
spi, spi,
nss, nss,
delay_ns: f, delay_ns,
} }
} }