From cea9f2bf57b4b3c32aa141d80e3a722586b99562 Mon Sep 17 00:00:00 2001 From: occheung Date: Wed, 20 Jan 2021 17:21:08 +0800 Subject: [PATCH 1/8] spi: owns delay --- src/lib.rs | 18 ++++++++++-------- src/spi.rs | 26 +++++++++++++++++--------- 2 files changed, 27 insertions(+), 17 deletions(-) diff --git a/src/lib.rs b/src/lib.rs index af883e9..d96cbaf 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -19,7 +19,7 @@ pub mod smoltcp_phy; pub const RAW_FRAME_LENGTH_MAX: usize = 1518; pub trait EthController { - fn init_dev(&mut self, delay: &mut impl DelayUs) -> Result<(), EthControllerError>; + fn init_dev(&mut self) -> Result<(), EthControllerError>; fn init_rxbuf(&mut self) -> Result<(), EthControllerError>; fn init_txbuf(&mut self) -> Result<(), EthControllerError>; fn receive_next(&mut self, is_poll: bool) -> Result; @@ -45,17 +45,19 @@ impl From for EthControllerError { /// Ethernet controller using SPI interface pub struct SpiEth, - NSS: OutputPin> { - spi_port: spi::SpiPort, + NSS: OutputPin, + Delay: DelayUs> { + spi_port: spi::SpiPort, rx_buf: rx::RxBuffer, tx_buf: tx::TxBuffer } impl , - NSS: OutputPin> SpiEth { - pub fn new(spi: SPI, nss: NSS) -> Self { + NSS: OutputPin, + Delay: DelayUs> SpiEth { + pub fn new(spi: SPI, nss: NSS, delay: Delay) -> Self { SpiEth { - spi_port: spi::SpiPort::new(spi, nss), + spi_port: spi::SpiPort::new(spi, nss, delay), rx_buf: rx::RxBuffer::new(), tx_buf: tx::TxBuffer::new() } @@ -63,8 +65,8 @@ impl , } impl , - NSS: OutputPin> EthController for SpiEth { - fn init_dev(&mut self, delay: &mut impl DelayUs) -> Result<(), EthControllerError> { + NSS: OutputPin, + Delay: DelayUs> EthController for SpiEth { // Write 0x1234 to EUDAST self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?; // Verify that EUDAST is 0x1234 diff --git a/src/spi.rs b/src/spi.rs index c2f5dcc..43aa18b 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -1,5 +1,5 @@ use embedded_hal::{ - blocking::spi::Transfer, + blocking::{spi::Transfer, delay::DelayUs}, digital::v2::OutputPin, }; @@ -52,9 +52,11 @@ pub mod addrs { /// Struct for SPI I/O interface on ENC424J600 /// Note: stm32f4xx_hal::spi's pins include: SCK, MISO, MOSI pub struct SpiPort, - NSS: OutputPin> { + NSS: OutputPin, + Delay: DelayUs> { spi: SPI, nss: NSS, + delay: Delay, } pub enum SpiPortError { @@ -63,14 +65,16 @@ pub enum SpiPortError { #[allow(unused_must_use)] impl , - NSS: OutputPin> SpiPort { + NSS: OutputPin, + Delay: DelayUs> SpiPort { // TODO: return as Result() - pub fn new(spi: SPI, mut nss: NSS) -> Self { + pub fn new(spi: SPI, mut nss: NSS, delay: Delay) -> Self { nss.set_high(); SpiPort { spi, - nss + nss, + delay } } @@ -115,6 +119,10 @@ impl , Ok(()) } + pub fn delay_us(&mut self, duration: u16) { + self.delay.delay_us(duration) + } + // TODO: Generalise transfer functions // TODO: (Make data read/write as reference to array) // Currently requires 1-byte addr, read/write data is only 1-byte @@ -131,17 +139,17 @@ impl , match self.spi.transfer(&mut buf) { Ok(_) => { // Disable chip select - cortex_m::asm::delay(10_u32); + self.delay_us(1); self.nss.set_high(); - cortex_m::asm::delay(5_u32); + self.delay_us(1); Ok(buf[2]) }, // TODO: Maybe too naive? Err(_) => { // Disable chip select - cortex_m::asm::delay(10_u32); + self.delay_us(1); self.nss.set_high(); - cortex_m::asm::delay(5_u32); + self.delay_us(1); Err(SpiPortError::TransferError) } } -- 2.42.0 From 056f812e6035351d5c7a66ec2ed8fc1de315f70b Mon Sep 17 00:00:00 2001 From: occheung Date: Wed, 20 Jan 2021 17:27:02 +0800 Subject: [PATCH 2/8] init: use delay from internal spi --- src/lib.rs | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/lib.rs b/src/lib.rs index d96cbaf..baf065f 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -67,6 +67,7 @@ impl , impl , NSS: OutputPin, Delay: DelayUs> EthController for SpiEth { + fn init_dev(&mut self) -> Result<(), EthControllerError> { // Write 0x1234 to EUDAST self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?; // Verify that EUDAST is 0x1234 @@ -83,14 +84,14 @@ impl , let econ2 = self.spi_port.read_reg_8b(spi::addrs::ECON2)?; self.spi_port.write_reg_8b(spi::addrs::ECON2, 0x10 | (econ2 & 0b11101111))?; // Wait for 25us - delay.delay_us(25_u16); + self.spi_port.delay_us(25_u16); // Verify that EUDAST is 0x0000 eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?; if eudast != 0x0000 { return Err(EthControllerError::GeneralError) } // Wait for 256us - delay.delay_us(256_u16); + self.spi_port.delay_us(256_u16); Ok(()) } -- 2.42.0 From eeeb162cc544670d4a339575f7f08999e56ae844 Mon Sep 17 00:00:00 2001 From: occheung Date: Thu, 21 Jan 2021 13:03:33 +0800 Subject: [PATCH 3/8] examples: updated --- examples/delay.rs | 33 +++++++++++++++++++++++++++++++++ examples/tcp_stm32f407.rs | 24 +++++++++++++++--------- examples/tx_stm32f407.rs | 21 +++++++++++++-------- 3 files changed, 61 insertions(+), 17 deletions(-) create mode 100644 examples/delay.rs diff --git a/examples/delay.rs b/examples/delay.rs new file mode 100644 index 0000000..d3bbbb3 --- /dev/null +++ b/examples/delay.rs @@ -0,0 +1,33 @@ +use embedded_hal::blocking::delay::{DelayMs, DelayUs}; + +pub struct AsmDelay { + frequency_us: u32, + frequency_ms: u32, +} + +impl AsmDelay { + pub fn new(freq: u32) -> AsmDelay { + AsmDelay { + frequency_us: (freq / 1_000_000), + frequency_ms: (freq / 1_000), + } + } +} + +impl DelayUs for AsmDelay +where + U: Into, +{ + fn delay_us(&mut self, us: U) { + cortex_m::asm::delay(self.frequency_us * us.into()) + } +} + +impl DelayMs for AsmDelay +where + U: Into, +{ + fn delay_ms(&mut self, ms: U) { + cortex_m::asm::delay(self.frequency_ms * ms.into()) + } +} \ No newline at end of file diff --git a/examples/tcp_stm32f407.rs b/examples/tcp_stm32f407.rs index b841517..a64b860 100644 --- a/examples/tcp_stm32f407.rs +++ b/examples/tcp_stm32f407.rs @@ -28,6 +28,9 @@ use smoltcp::socket::{SocketSet, TcpSocket, TcpSocketBuffer}; use core::str; use core::fmt::Write; +mod delay; +use delay::AsmDelay; + /// Timer use core::cell::RefCell; use cortex_m::interrupt::Mutex; @@ -80,7 +83,9 @@ use stm32f4xx_hal::{ }; type BoosterSpiEth = enc424j600::SpiEth< Spi>, PA6>, PA7>)>, - PA4>>; + PA4>, + AsmDelay +>; pub struct NetStorage { ip_addrs: [IpCidr; 1], @@ -122,7 +127,8 @@ const APP: () = { .pclk1(42.mhz()) .require_pll48clk() .freeze(); - let mut delay = Delay::new(c.core.SYST, clocks); + let asm_delay = AsmDelay::new(clocks.sysclk().0); + let mut hal_delay = Delay::new(c.core.SYST, clocks); // Init ITM let mut itm = c.core.ITM; @@ -142,7 +148,7 @@ const APP: () = { // Map SPISEL: see Table 1, NIC100 Manual let mut spisel = gpioa.pa1.into_push_pull_output(); spisel.set_high().unwrap(); - delay.delay_ms(1_u32); + hal_delay.delay_ms(1_u32); spisel.set_low().unwrap(); // Create SPI1 for HAL @@ -153,11 +159,11 @@ const APP: () = { enc424j600::spi::interfaces::SPI_MODE, Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ), clocks); - enc424j600::SpiEth::new(spi_eth_port, spi1_nss) + enc424j600::SpiEth::new(spi_eth_port, spi1_nss, asm_delay) }; // Init controller - match spi_eth.init_dev(&mut delay) { + match spi_eth.init_dev() { Ok(_) => { iprintln!(stim0, "Initializing Ethernet...") } @@ -168,7 +174,7 @@ const APP: () = { // Read MAC let mut eth_mac_addr: [u8; 6] = [0; 6]; - spi_eth.read_from_mac(&mut eth_mac_addr); + spi_eth.read_from_mac(&mut eth_mac_addr).unwrap(); for i in 0..6 { let byte = eth_mac_addr[i]; match i { @@ -180,8 +186,8 @@ const APP: () = { } // Init Rx/Tx buffers - spi_eth.init_rxbuf(); - spi_eth.init_txbuf(); + spi_eth.init_rxbuf().unwrap(); + spi_eth.init_txbuf().unwrap(); iprintln!(stim0, "Ethernet controller initialized"); // Init smoltcp interface @@ -205,7 +211,7 @@ const APP: () = { // Setup SysTick after releasing SYST from Delay // Reference to stm32-eth:examples/ip.rs - timer_setup(delay.free(), clocks); + timer_setup(hal_delay.free(), clocks); iprintln!(stim0, "Timer initialized"); init::LateResources { diff --git a/examples/tx_stm32f407.rs b/examples/tx_stm32f407.rs index 4dd10ac..c88b5a0 100644 --- a/examples/tx_stm32f407.rs +++ b/examples/tx_stm32f407.rs @@ -20,6 +20,9 @@ use stm32f4xx_hal::{ use enc424j600; use enc424j600::EthController; +mod delay; +use delay::AsmDelay; + /// use stm32f4xx_hal::{ stm32::SPI1, @@ -30,7 +33,8 @@ use stm32f4xx_hal::{ }; type BoosterSpiEth = enc424j600::SpiEth< Spi>, PA6>, PA7>)>, - PA4>>; + PA4>, + AsmDelay>; #[rtic::app(device = stm32f4xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)] const APP: () = { @@ -54,6 +58,7 @@ const APP: () = { //.pclk2(64.mhz()) .require_pll48clk() .freeze(); + let asm_delay = AsmDelay::new(clocks.sysclk().0); let mut delay = Delay::new(c.core.SYST, clocks); // Init ITM @@ -82,11 +87,11 @@ const APP: () = { enc424j600::spi::interfaces::SPI_MODE, Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ), clocks); - enc424j600::SpiEth::new(spi_eth_port, spi1_nss) + enc424j600::SpiEth::new(spi_eth_port, spi1_nss, asm_delay) }; // Init - match spi_eth.init_dev(&mut delay) { + match spi_eth.init_dev() { Ok(_) => { iprintln!(stim0, "Initializing Ethernet...") } @@ -97,7 +102,7 @@ const APP: () = { // Read MAC let mut eth_mac_addr: [u8; 6] = [0; 6]; - spi_eth.read_from_mac(&mut eth_mac_addr); + spi_eth.read_from_mac(&mut eth_mac_addr).unwrap(); for i in 0..6 { let byte = eth_mac_addr[i]; match i { @@ -109,8 +114,8 @@ const APP: () = { } // Init Rx/Tx buffers - spi_eth.init_rxbuf(); - spi_eth.init_txbuf(); + spi_eth.init_rxbuf().unwrap(); + spi_eth.init_txbuf().unwrap(); iprintln!(stim0, "Ethernet controller initialized"); init::LateResources { @@ -130,7 +135,7 @@ const APP: () = { 0x08, 0x00, 0x06, 0x04, 0x00, 0x01, 0x08, 0x60, 0x6e, 0x44, 0x42, 0x95, 0xc0, 0xa8, 0x01, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xa8, - 0x01, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x7d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0xd0, 0x85, 0x9f ]; @@ -152,7 +157,7 @@ const APP: () = { _ => () }; } - c.resources.spi_eth.send_raw_packet(ð_tx_packet); + c.resources.spi_eth.send_raw_packet(ð_tx_packet).unwrap(); iprintln!(stim0, "Packet sent"); c.resources.delay.delay_ms(100_u32); } -- 2.42.0 From b8094f84f37d01454ec3c92f5ae4a2329c65d375 Mon Sep 17 00:00:00 2001 From: occheung Date: Thu, 21 Jan 2021 13:18:30 +0800 Subject: [PATCH 4/8] example/tx: arp revert modification --- examples/tx_stm32f407.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/tx_stm32f407.rs b/examples/tx_stm32f407.rs index c88b5a0..da8d7fc 100644 --- a/examples/tx_stm32f407.rs +++ b/examples/tx_stm32f407.rs @@ -135,7 +135,7 @@ const APP: () = { 0x08, 0x00, 0x06, 0x04, 0x00, 0x01, 0x08, 0x60, 0x6e, 0x44, 0x42, 0x95, 0xc0, 0xa8, 0x01, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xa8, - 0x01, 0x7d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0xd0, 0x85, 0x9f ]; -- 2.42.0 From c146eb155d9bacb9541e12483851040be9cb2e39 Mon Sep 17 00:00:00 2001 From: occheung Date: Fri, 22 Jan 2021 14:35:32 +0800 Subject: [PATCH 5/8] examples: remove duplicate delay --- examples/delay.rs | 1 + examples/tcp_stm32f407.rs | 8 +++----- examples/tx_stm32f407.rs | 10 ++++------ 3 files changed, 8 insertions(+), 11 deletions(-) diff --git a/examples/delay.rs b/examples/delay.rs index d3bbbb3..204fe0a 100644 --- a/examples/delay.rs +++ b/examples/delay.rs @@ -1,5 +1,6 @@ use embedded_hal::blocking::delay::{DelayMs, DelayUs}; +#[derive(Clone, Copy)] pub struct AsmDelay { frequency_us: u32, frequency_ms: u32, diff --git a/examples/tcp_stm32f407.rs b/examples/tcp_stm32f407.rs index a64b860..9727c4e 100644 --- a/examples/tcp_stm32f407.rs +++ b/examples/tcp_stm32f407.rs @@ -13,7 +13,6 @@ use stm32f4xx_hal::{ gpio::GpioExt, time::U32Ext, stm32::ITM, - delay::Delay, spi::Spi, time::Hertz }; @@ -127,8 +126,7 @@ const APP: () = { .pclk1(42.mhz()) .require_pll48clk() .freeze(); - let asm_delay = AsmDelay::new(clocks.sysclk().0); - let mut hal_delay = Delay::new(c.core.SYST, clocks); + let mut asm_delay = AsmDelay::new(clocks.sysclk().0); // Init ITM let mut itm = c.core.ITM; @@ -148,7 +146,7 @@ const APP: () = { // Map SPISEL: see Table 1, NIC100 Manual let mut spisel = gpioa.pa1.into_push_pull_output(); spisel.set_high().unwrap(); - hal_delay.delay_ms(1_u32); + asm_delay.delay_ms(1_u32); spisel.set_low().unwrap(); // Create SPI1 for HAL @@ -211,7 +209,7 @@ const APP: () = { // Setup SysTick after releasing SYST from Delay // Reference to stm32-eth:examples/ip.rs - timer_setup(hal_delay.free(), clocks); + timer_setup(c.core.SYST, clocks); iprintln!(stim0, "Timer initialized"); init::LateResources { diff --git a/examples/tx_stm32f407.rs b/examples/tx_stm32f407.rs index da8d7fc..fb76a6a 100644 --- a/examples/tx_stm32f407.rs +++ b/examples/tx_stm32f407.rs @@ -13,7 +13,6 @@ use stm32f4xx_hal::{ gpio::GpioExt, time::U32Ext, stm32::ITM, - delay::Delay, spi::Spi, time::Hertz }; @@ -40,7 +39,7 @@ type BoosterSpiEth = enc424j600::SpiEth< const APP: () = { struct Resources { spi_eth: BoosterSpiEth, - delay: Delay, + delay: AsmDelay, itm: ITM, } @@ -58,8 +57,7 @@ const APP: () = { //.pclk2(64.mhz()) .require_pll48clk() .freeze(); - let asm_delay = AsmDelay::new(clocks.sysclk().0); - let mut delay = Delay::new(c.core.SYST, clocks); + let mut asm_delay = AsmDelay::new(clocks.sysclk().0); // Init ITM let mut itm = c.core.ITM; @@ -78,7 +76,7 @@ const APP: () = { // Map SPISEL: see Table 1, NIC100 Manual let mut spisel = gpioa.pa1.into_push_pull_output(); spisel.set_high().unwrap(); - delay.delay_ms(1_u32); + asm_delay.delay_ms(1_u32); spisel.set_low().unwrap(); // Create SPI1 for HAL let mut spi_eth = { @@ -120,7 +118,7 @@ const APP: () = { init::LateResources { spi_eth, - delay, + delay: asm_delay, itm, } } -- 2.42.0 From 366ff1c80edfef3fa78c57baed9230a98e21b9dd Mon Sep 17 00:00:00 2001 From: occheung Date: Fri, 22 Jan 2021 17:44:02 +0800 Subject: [PATCH 6/8] * Changed delay source from DelayUs from embedded-hal to user-defined closure * Updated examples - Removed delay.rs - Removed over-obvious comments --- examples/delay.rs | 34 ---------------------------------- examples/tcp_stm32f407.rs | 12 ++++++++++-- examples/tx_stm32f407.rs | 20 +++++++++++--------- src/lib.rs | 19 ++++++++----------- src/spi.rs | 24 ++++++++++++------------ 5 files changed, 41 insertions(+), 68 deletions(-) delete mode 100644 examples/delay.rs diff --git a/examples/delay.rs b/examples/delay.rs deleted file mode 100644 index 204fe0a..0000000 --- a/examples/delay.rs +++ /dev/null @@ -1,34 +0,0 @@ -use embedded_hal::blocking::delay::{DelayMs, DelayUs}; - -#[derive(Clone, Copy)] -pub struct AsmDelay { - frequency_us: u32, - frequency_ms: u32, -} - -impl AsmDelay { - pub fn new(freq: u32) -> AsmDelay { - AsmDelay { - frequency_us: (freq / 1_000_000), - frequency_ms: (freq / 1_000), - } - } -} - -impl DelayUs for AsmDelay -where - U: Into, -{ - fn delay_us(&mut self, us: U) { - cortex_m::asm::delay(self.frequency_us * us.into()) - } -} - -impl DelayMs for AsmDelay -where - U: Into, -{ - fn delay_ms(&mut self, ms: U) { - cortex_m::asm::delay(self.frequency_ms * ms.into()) - } -} \ No newline at end of file diff --git a/examples/tcp_stm32f407.rs b/examples/tcp_stm32f407.rs index 9727c4e..d734160 100644 --- a/examples/tcp_stm32f407.rs +++ b/examples/tcp_stm32f407.rs @@ -83,7 +83,7 @@ use stm32f4xx_hal::{ type BoosterSpiEth = enc424j600::SpiEth< Spi>, PA6>, PA7>)>, PA4>, - AsmDelay + fn(u32) -> () >; pub struct NetStorage { @@ -99,6 +99,10 @@ static mut NET_STORE: NetStorage = NetStorage { neighbor_cache: [None; 8], }; +pub fn delay_ns(time_ns: u32) { + cortex_m::asm::delay((time_ns*168_000_000)/1_000_000_000 + 1) +} + #[rtic::app(device = stm32f4xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)] const APP: () = { struct Resources { @@ -157,7 +161,11 @@ const APP: () = { enc424j600::spi::interfaces::SPI_MODE, Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ), clocks); - enc424j600::SpiEth::new(spi_eth_port, spi1_nss, asm_delay) + + let delay_ns_fp: fn(u32) -> () = |time_ns| { + cortex_m::asm::delay((time_ns*21)/125 + 1) + }; + enc424j600::SpiEth::new(spi_eth_port, spi1_nss, delay_ns_fp) }; // Init controller diff --git a/examples/tx_stm32f407.rs b/examples/tx_stm32f407.rs index fb76a6a..6c36402 100644 --- a/examples/tx_stm32f407.rs +++ b/examples/tx_stm32f407.rs @@ -13,15 +13,13 @@ use stm32f4xx_hal::{ gpio::GpioExt, time::U32Ext, stm32::ITM, + delay::Delay, spi::Spi, time::Hertz }; use enc424j600; use enc424j600::EthController; -mod delay; -use delay::AsmDelay; - /// use stm32f4xx_hal::{ stm32::SPI1, @@ -33,13 +31,13 @@ use stm32f4xx_hal::{ type BoosterSpiEth = enc424j600::SpiEth< Spi>, PA6>, PA7>)>, PA4>, - AsmDelay>; + fn(u32)>; #[rtic::app(device = stm32f4xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)] const APP: () = { struct Resources { spi_eth: BoosterSpiEth, - delay: AsmDelay, + delay: Delay, itm: ITM, } @@ -57,7 +55,7 @@ const APP: () = { //.pclk2(64.mhz()) .require_pll48clk() .freeze(); - let mut asm_delay = AsmDelay::new(clocks.sysclk().0); + let mut delay = Delay::new(c.core.SYST, clocks); // Init ITM let mut itm = c.core.ITM; @@ -76,7 +74,7 @@ const APP: () = { // Map SPISEL: see Table 1, NIC100 Manual let mut spisel = gpioa.pa1.into_push_pull_output(); spisel.set_high().unwrap(); - asm_delay.delay_ms(1_u32); + delay.delay_ms(1_u32); spisel.set_low().unwrap(); // Create SPI1 for HAL let mut spi_eth = { @@ -85,7 +83,11 @@ const APP: () = { enc424j600::spi::interfaces::SPI_MODE, Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ), clocks); - enc424j600::SpiEth::new(spi_eth_port, spi1_nss, asm_delay) + + let delay_ns_fp: fn(u32) -> () = |time_ns| { + cortex_m::asm::delay((time_ns*21)/125 + 1) + }; + enc424j600::SpiEth::new(spi_eth_port, spi1_nss, delay_ns_fp) }; // Init @@ -118,7 +120,7 @@ const APP: () = { init::LateResources { spi_eth, - delay: asm_delay, + delay, itm, } } diff --git a/src/lib.rs b/src/lib.rs index baf065f..e99cefa 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -4,7 +4,6 @@ pub mod spi; use embedded_hal::{ blocking::{ spi::Transfer, - delay::DelayUs, }, digital::v2::OutputPin, }; @@ -46,18 +45,18 @@ impl From for EthControllerError { /// Ethernet controller using SPI interface pub struct SpiEth, NSS: OutputPin, - Delay: DelayUs> { - spi_port: spi::SpiPort, + F: FnMut(u32) -> ()> { + spi_port: spi::SpiPort, rx_buf: rx::RxBuffer, tx_buf: tx::TxBuffer } impl , NSS: OutputPin, - Delay: DelayUs> SpiEth { - pub fn new(spi: SPI, nss: NSS, delay: Delay) -> Self { + F: FnMut(u32) -> ()> SpiEth { + pub fn new(spi: SPI, nss: NSS, f: F) -> Self { SpiEth { - spi_port: spi::SpiPort::new(spi, nss, delay), + spi_port: spi::SpiPort::new(spi, nss, f), rx_buf: rx::RxBuffer::new(), tx_buf: tx::TxBuffer::new() } @@ -66,7 +65,7 @@ impl , impl , NSS: OutputPin, - Delay: DelayUs> EthController for SpiEth { + F: FnMut(u32) -> ()> EthController for SpiEth { fn init_dev(&mut self) -> Result<(), EthControllerError> { // Write 0x1234 to EUDAST self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?; @@ -83,15 +82,13 @@ impl , // Set ETHRST (ECON2<4>) to 1 let econ2 = self.spi_port.read_reg_8b(spi::addrs::ECON2)?; self.spi_port.write_reg_8b(spi::addrs::ECON2, 0x10 | (econ2 & 0b11101111))?; - // Wait for 25us - self.spi_port.delay_us(25_u16); + self.spi_port.delay_us(25); // Verify that EUDAST is 0x0000 eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?; if eudast != 0x0000 { return Err(EthControllerError::GeneralError) } - // Wait for 256us - self.spi_port.delay_us(256_u16); + self.spi_port.delay_us(256); Ok(()) } diff --git a/src/spi.rs b/src/spi.rs index 43aa18b..6bb1d37 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -1,5 +1,5 @@ use embedded_hal::{ - blocking::{spi::Transfer, delay::DelayUs}, + blocking::{spi::Transfer}, digital::v2::OutputPin, }; @@ -53,10 +53,10 @@ pub mod addrs { /// Note: stm32f4xx_hal::spi's pins include: SCK, MISO, MOSI pub struct SpiPort, NSS: OutputPin, - Delay: DelayUs> { + F: FnMut(u32) -> ()> { spi: SPI, nss: NSS, - delay: Delay, + delay_ns: F, } pub enum SpiPortError { @@ -66,15 +66,15 @@ pub enum SpiPortError { #[allow(unused_must_use)] impl , NSS: OutputPin, - Delay: DelayUs> SpiPort { + F: FnMut(u32) -> ()> SpiPort { // TODO: return as Result() - pub fn new(spi: SPI, mut nss: NSS, delay: Delay) -> Self { + pub fn new(spi: SPI, mut nss: NSS, f: F) -> Self { nss.set_high(); SpiPort { spi, nss, - delay + delay_ns: f, } } @@ -119,8 +119,8 @@ impl , Ok(()) } - pub fn delay_us(&mut self, duration: u16) { - self.delay.delay_us(duration) + pub fn delay_us(&mut self, duration: u32) { + (self.delay_ns)(duration * 1000) } // TODO: Generalise transfer functions @@ -139,17 +139,17 @@ impl , match self.spi.transfer(&mut buf) { Ok(_) => { // Disable chip select - self.delay_us(1); + (self.delay_ns)(60); self.nss.set_high(); - self.delay_us(1); + (self.delay_ns)(30); Ok(buf[2]) }, // TODO: Maybe too naive? Err(_) => { // Disable chip select - self.delay_us(1); + (self.delay_ns)(60); self.nss.set_high(); - self.delay_us(1); + (self.delay_ns)(30); Err(SpiPortError::TransferError) } } -- 2.42.0 From d557e2542db703524f06eaba5947fe3fd689f17e Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 25 Jan 2021 10:47:21 +0800 Subject: [PATCH 7/8] Modify changes: - Revert unwrap() addition to examples - Remove redundant bracket * Changed closure variable to delay_ns for clarity --- examples/tcp_stm32f407.rs | 6 +++--- examples/tx_stm32f407.rs | 8 ++++---- src/lib.rs | 4 ++-- src/spi.rs | 6 +++--- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/examples/tcp_stm32f407.rs b/examples/tcp_stm32f407.rs index d734160..10e4e7a 100644 --- a/examples/tcp_stm32f407.rs +++ b/examples/tcp_stm32f407.rs @@ -180,7 +180,7 @@ const APP: () = { // Read MAC let mut eth_mac_addr: [u8; 6] = [0; 6]; - spi_eth.read_from_mac(&mut eth_mac_addr).unwrap(); + spi_eth.read_from_mac(&mut eth_mac_addr); for i in 0..6 { let byte = eth_mac_addr[i]; match i { @@ -192,8 +192,8 @@ const APP: () = { } // Init Rx/Tx buffers - spi_eth.init_rxbuf().unwrap(); - spi_eth.init_txbuf().unwrap(); + spi_eth.init_rxbuf(); + spi_eth.init_txbuf(); iprintln!(stim0, "Ethernet controller initialized"); // Init smoltcp interface diff --git a/examples/tx_stm32f407.rs b/examples/tx_stm32f407.rs index 6c36402..93d6ab9 100644 --- a/examples/tx_stm32f407.rs +++ b/examples/tx_stm32f407.rs @@ -102,7 +102,7 @@ const APP: () = { // Read MAC let mut eth_mac_addr: [u8; 6] = [0; 6]; - spi_eth.read_from_mac(&mut eth_mac_addr).unwrap(); + spi_eth.read_from_mac(&mut eth_mac_addr); for i in 0..6 { let byte = eth_mac_addr[i]; match i { @@ -114,8 +114,8 @@ const APP: () = { } // Init Rx/Tx buffers - spi_eth.init_rxbuf().unwrap(); - spi_eth.init_txbuf().unwrap(); + spi_eth.init_rxbuf(); + spi_eth.init_txbuf(); iprintln!(stim0, "Ethernet controller initialized"); init::LateResources { @@ -157,7 +157,7 @@ const APP: () = { _ => () }; } - c.resources.spi_eth.send_raw_packet(ð_tx_packet).unwrap(); + c.resources.spi_eth.send_raw_packet(ð_tx_packet); iprintln!(stim0, "Packet sent"); c.resources.delay.delay_ms(100_u32); } diff --git a/src/lib.rs b/src/lib.rs index e99cefa..71e6e7c 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -54,9 +54,9 @@ pub struct SpiEth, impl , NSS: OutputPin, F: FnMut(u32) -> ()> SpiEth { - pub fn new(spi: SPI, nss: NSS, f: F) -> Self { + pub fn new(spi: SPI, nss: NSS, delay_ns: F) -> Self { SpiEth { - spi_port: spi::SpiPort::new(spi, nss, f), + spi_port: spi::SpiPort::new(spi, nss, delay_ns), rx_buf: rx::RxBuffer::new(), tx_buf: tx::TxBuffer::new() } diff --git a/src/spi.rs b/src/spi.rs index 6bb1d37..a5dd23c 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -1,5 +1,5 @@ use embedded_hal::{ - blocking::{spi::Transfer}, + blocking::spi::Transfer, digital::v2::OutputPin, }; @@ -68,13 +68,13 @@ impl , NSS: OutputPin, F: FnMut(u32) -> ()> SpiPort { // TODO: return as Result() - pub fn new(spi: SPI, mut nss: NSS, f: F) -> Self { + pub fn new(spi: SPI, mut nss: NSS, delay_ns: F) -> Self { nss.set_high(); SpiPort { spi, nss, - delay_ns: f, + delay_ns, } } -- 2.42.0 From 5bdfd21e93b7afe6d53ba2bb7fe117ceca5af032 Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 25 Jan 2021 11:47:05 +0800 Subject: [PATCH 8/8] example/tcp: fix delay reference --- examples/tcp_stm32f407.rs | 14 ++++---------- examples/tx_stm32f407.rs | 4 ++-- 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/examples/tcp_stm32f407.rs b/examples/tcp_stm32f407.rs index 10e4e7a..80e3278 100644 --- a/examples/tcp_stm32f407.rs +++ b/examples/tcp_stm32f407.rs @@ -13,6 +13,7 @@ use stm32f4xx_hal::{ gpio::GpioExt, time::U32Ext, stm32::ITM, + delay::Delay, spi::Spi, time::Hertz }; @@ -27,9 +28,6 @@ use smoltcp::socket::{SocketSet, TcpSocket, TcpSocketBuffer}; use core::str; use core::fmt::Write; -mod delay; -use delay::AsmDelay; - /// Timer use core::cell::RefCell; use cortex_m::interrupt::Mutex; @@ -99,10 +97,6 @@ static mut NET_STORE: NetStorage = NetStorage { neighbor_cache: [None; 8], }; -pub fn delay_ns(time_ns: u32) { - cortex_m::asm::delay((time_ns*168_000_000)/1_000_000_000 + 1) -} - #[rtic::app(device = stm32f4xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)] const APP: () = { struct Resources { @@ -130,7 +124,7 @@ const APP: () = { .pclk1(42.mhz()) .require_pll48clk() .freeze(); - let mut asm_delay = AsmDelay::new(clocks.sysclk().0); + let mut delay = Delay::new(c.core.SYST, clocks); // Init ITM let mut itm = c.core.ITM; @@ -150,7 +144,7 @@ const APP: () = { // Map SPISEL: see Table 1, NIC100 Manual let mut spisel = gpioa.pa1.into_push_pull_output(); spisel.set_high().unwrap(); - asm_delay.delay_ms(1_u32); + delay.delay_ms(1_u32); spisel.set_low().unwrap(); // Create SPI1 for HAL @@ -217,7 +211,7 @@ const APP: () = { // Setup SysTick after releasing SYST from Delay // Reference to stm32-eth:examples/ip.rs - timer_setup(c.core.SYST, clocks); + timer_setup(delay.free(), clocks); iprintln!(stim0, "Timer initialized"); init::LateResources { diff --git a/examples/tx_stm32f407.rs b/examples/tx_stm32f407.rs index 93d6ab9..268e254 100644 --- a/examples/tx_stm32f407.rs +++ b/examples/tx_stm32f407.rs @@ -84,10 +84,10 @@ const APP: () = { Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ), clocks); - let delay_ns_fp: fn(u32) -> () = |time_ns| { + let delay_ns: fn(u32) -> () = |time_ns| { cortex_m::asm::delay((time_ns*21)/125 + 1) }; - enc424j600::SpiEth::new(spi_eth_port, spi1_nss, delay_ns_fp) + enc424j600::SpiEth::new(spi_eth_port, spi1_nss, delay_ns) }; // Init -- 2.42.0