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ENC424J600
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Improve mod & struct visibility & hierarchy #10

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harry wants to merge 4 commits from fix-visibility into master
pull from: fix-visibility
merge into: renet:master
Conversation 0 Commits 4 Files Changed 6 +35 -69
6 changed files with 35 additions and 69 deletions
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10
examples/tcp_stm32f407.rs
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@ -17,7 +17,7 @@ use stm32f4xx_hal::{
spi::Spi, spi::Spi,
time::Hertz time::Hertz
}; };
use enc424j600::smoltcp_phy; use enc424j600::SmoltcpDevice;
use smoltcp::wire::{ use smoltcp::wire::{
EthernetAddress, IpAddress, IpCidr, Ipv6Cidr EthernetAddress, IpAddress, IpCidr, Ipv6Cidr
@ -100,7 +100,7 @@ const APP: () = {
struct Resources { struct Resources {
eth_iface: EthernetInterface< eth_iface: EthernetInterface<
'static, 'static,
smoltcp_phy::SmoltcpDevice<SpiEth>>, SmoltcpDevice<SpiEth>>,
itm: ITM itm: ITM
} }
@ -148,8 +148,8 @@ const APP: () = {
let mut spi_eth = { let mut spi_eth = {
let spi_eth_port = Spi::spi1( let spi_eth_port = Spi::spi1(
spi1, (spi1_sck, spi1_miso, spi1_mosi), spi1, (spi1_sck, spi1_miso, spi1_mosi),
enc424j600::spi::interfaces::SPI_MODE, enc424j600::SpiInterfaces::SPI_MODE,
Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ), Hertz(enc424j600::SpiInterfaces::SPI_CLOCK_FREQ),
clocks); clocks);
SpiEth::new(spi_eth_port, spi1_nss) SpiEth::new(spi_eth_port, spi1_nss)
@ -186,7 +186,7 @@ const APP: () = {
// Init smoltcp interface // Init smoltcp interface
let eth_iface = { let eth_iface = {
let device = smoltcp_phy::SmoltcpDevice::new(spi_eth); let device = SmoltcpDevice::new(spi_eth);
let store = unsafe { &mut NET_STORE }; let store = unsafe { &mut NET_STORE };
store.ip_addrs[0] = IpCidr::new(IpAddress::v4(192, 168, 1, 77), 24); store.ip_addrs[0] = IpCidr::new(IpAddress::v4(192, 168, 1, 77), 24);

6
examples/tx_stm32f407.rs
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@ -79,8 +79,8 @@ const APP: () = {
let mut spi_eth = { let mut spi_eth = {
let spi_eth_port = Spi::spi1( let spi_eth_port = Spi::spi1(
spi1, (spi1_sck, spi1_miso, spi1_mosi), spi1, (spi1_sck, spi1_miso, spi1_mosi),
enc424j600::spi::interfaces::SPI_MODE, enc424j600::SpiInterfaces::SPI_MODE,
Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ), Hertz(enc424j600::SpiInterfaces::SPI_CLOCK_FREQ),
clocks); clocks);
SpiEth::new(spi_eth_port, spi1_nss) SpiEth::new(spi_eth_port, spi1_nss)
@ -137,7 +137,7 @@ const APP: () = {
0x00, 0x00, 0x00, 0x00, 0x69, 0xd0, 0x85, 0x9f 0x00, 0x00, 0x00, 0x00, 0x69, 0xd0, 0x85, 0x9f
]; ];
loop { loop {
let mut eth_tx_packet = enc424j600::tx::TxPacket::new(); let mut eth_tx_packet = enc424j600::TxPacket::new();
eth_tx_packet.update_frame(&eth_tx_dat, 64); eth_tx_packet.update_frame(&eth_tx_dat, 64);
iprint!(stim0, iprint!(stim0,
"Sending packet (len={:}): ", eth_tx_packet.get_frame_length()); "Sending packet (len={:}): ", eth_tx_packet.get_frame_length());

32
src/lib.rs
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@ -1,6 +1,7 @@
#![no_std] #![no_std]
pub mod spi; mod spi;
pub use crate::spi::interfaces as SpiInterfaces;
use embedded_hal::{ use embedded_hal::{
blocking::{ blocking::{
spi::Transfer, spi::Transfer,
@ -9,11 +10,16 @@ use embedded_hal::{
digital::v2::OutputPin, digital::v2::OutputPin,
}; };
pub mod rx; mod rx;
pub mod tx; mod tx;
pub use crate::{
rx::RxPacket, tx::TxPacket,
};
#[cfg(feature="smoltcp")] #[cfg(feature="smoltcp")]
pub mod smoltcp_phy; pub mod smoltcp_phy;
#[cfg(feature="smoltcp")]
pub use crate::smoltcp_phy::SmoltcpDevice;
#[cfg(feature="nal")] #[cfg(feature="nal")]
pub mod nal; pub mod nal;
@ -100,9 +106,9 @@ impl <SPI: Transfer<u8>,
pub fn init_rxbuf(&mut self) -> Result<(), Error> { pub fn init_rxbuf(&mut self) -> Result<(), Error> {
// Set ERXST pointer // Set ERXST pointer
self.spi_port.write_reg_16b(spi::addrs::ERXST, self.rx_buf.get_start_addr())?; self.spi_port.write_reg_16b(spi::addrs::ERXST, self.rx_buf.start_addr)?;
// Set ERXTAIL pointer // Set ERXTAIL pointer
self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, self.rx_buf.get_tail_addr())?; self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, self.rx_buf.tail_addr)?;
// Set MAMXFL to maximum number of bytes in each accepted packet // Set MAMXFL to maximum number of bytes in each accepted packet
self.spi_port.write_reg_16b(spi::addrs::MAMXFL, RAW_FRAME_LENGTH_MAX as u16)?; self.spi_port.write_reg_16b(spi::addrs::MAMXFL, RAW_FRAME_LENGTH_MAX as u16)?;
// Enable RX - set RXEN (ECON1<0>) to 1 // Enable RX - set RXEN (ECON1<0>) to 1
@ -163,11 +169,11 @@ impl <SPI: Transfer<u8>,
} }
} }
// Set ERXRDPT pointer to next_addr // Set ERXRDPT pointer to next_addr
self.spi_port.write_reg_16b(spi::addrs::ERXRDPT, self.rx_buf.get_next_addr())?; self.spi_port.write_reg_16b(spi::addrs::ERXRDPT, self.rx_buf.next_addr)?;
// Read 2 bytes to update next_addr // Read 2 bytes to update next_addr
let mut next_addr_buf = [0; 3]; let mut next_addr_buf = [0; 3];
self.spi_port.read_rxdat(&mut next_addr_buf, 2)?; self.spi_port.read_rxdat(&mut next_addr_buf, 2)?;
self.rx_buf.set_next_addr((next_addr_buf[1] as u16) | ((next_addr_buf[2] as u16) << 8)); self.rx_buf.next_addr = (next_addr_buf[1] as u16) | ((next_addr_buf[2] as u16) << 8);
// Read 6 bytes to update rsv // Read 6 bytes to update rsv
let mut rsv_buf = [0; 7]; let mut rsv_buf = [0; 7];
self.spi_port.read_rxdat(&mut rsv_buf, 6)?; self.spi_port.read_rxdat(&mut rsv_buf, 6)?;
@ -184,8 +190,8 @@ impl <SPI: Transfer<u8>,
// Set ERXTAIL pointer to (next_addr - 2) // Set ERXTAIL pointer to (next_addr - 2)
// * Assume head, tail, next and wrap addresses are word-aligned (even) // * Assume head, tail, next and wrap addresses are word-aligned (even)
// - If next_addr is at least (start_addr+2), then set tail pointer to the word right before next_addr // - If next_addr is at least (start_addr+2), then set tail pointer to the word right before next_addr
if self.rx_buf.get_next_addr() > self.rx_buf.get_start_addr() { if self.rx_buf.next_addr > self.rx_buf.start_addr {
self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, self.rx_buf.get_next_addr() - 2)?; self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, self.rx_buf.next_addr - 2)?;
// - Otherwise, next_addr will wrap, so set tail pointer to the last word address of RX buffer // - Otherwise, next_addr will wrap, so set tail pointer to the last word address of RX buffer
} else { } else {
self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, rx::RX_MAX_ADDRESS - 1)?; self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, rx::RX_MAX_ADDRESS - 1)?;
@ -199,14 +205,14 @@ impl <SPI: Transfer<u8>,
/// Send an established packet /// Send an established packet
fn send_packet(&mut self, packet: &tx::TxPacket) -> Result<(), Error> { fn send_packet(&mut self, packet: &tx::TxPacket) -> Result<(), Error> {
// Set EGPWRPT pointer to next_addr // Set EGPWRPT pointer to next_addr
self.spi_port.write_reg_16b(spi::addrs::EGPWRPT, self.tx_buf.get_next_addr())?; self.spi_port.write_reg_16b(spi::addrs::EGPWRPT, self.tx_buf.next_addr)?;
// Copy packet data to SRAM Buffer // Copy packet data to SRAM Buffer
// 1-byte Opcode is included // 1-byte Opcode is included
let mut txdat_buf: [u8; RAW_FRAME_LENGTH_MAX + 1] = [0; RAW_FRAME_LENGTH_MAX + 1]; let mut txdat_buf: [u8; RAW_FRAME_LENGTH_MAX + 1] = [0; RAW_FRAME_LENGTH_MAX + 1];
packet.write_frame_to(&mut txdat_buf[1..]); packet.write_frame_to(&mut txdat_buf[1..]);
self.spi_port.write_txdat(&mut txdat_buf, packet.get_frame_length())?; self.spi_port.write_txdat(&mut txdat_buf, packet.get_frame_length())?;
// Set ETXST to packet start address // Set ETXST to packet start address
self.spi_port.write_reg_16b(spi::addrs::ETXST, self.tx_buf.get_next_addr())?; self.spi_port.write_reg_16b(spi::addrs::ETXST, self.tx_buf.next_addr)?;
// Set ETXLEN to packet length // Set ETXLEN to packet length
self.spi_port.write_reg_16b(spi::addrs::ETXLEN, packet.get_frame_length() as u16)?; self.spi_port.write_reg_16b(spi::addrs::ETXLEN, packet.get_frame_length() as u16)?;
// Send packet - set TXRTS (ECON1<1>) to start transmission // Send packet - set TXRTS (ECON1<1>) to start transmission
@ -220,8 +226,8 @@ impl <SPI: Transfer<u8>,
// (See: Register 9-2, ENC424J600 Data Sheet) // (See: Register 9-2, ENC424J600 Data Sheet)
// Update TX buffer start address // Update TX buffer start address
// * Assume TX buffer consumes the entire general-purpose SRAM block // * Assume TX buffer consumes the entire general-purpose SRAM block
self.tx_buf.set_next_addr((self.tx_buf.get_next_addr() + packet.get_frame_length() as u16) % self.tx_buf.next_addr = (self.tx_buf.next_addr + packet.get_frame_length() as u16) %
self.rx_buf.get_start_addr() - self.tx_buf.get_start_addr()); self.rx_buf.start_addr - self.tx_buf.start_addr;
Ok(()) Ok(())
} }
} }

27
src/rx.rs
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@ -11,9 +11,9 @@ pub const RSV_LENGTH: usize = 6;
/// Struct for RX Buffer on the hardware /// Struct for RX Buffer on the hardware
/// TODO: Should be a singleton /// TODO: Should be a singleton
pub struct RxBuffer { pub struct RxBuffer {
start_addr: u16, pub start_addr: u16,
next_addr: u16, pub next_addr: u16,
tail_addr: u16 pub tail_addr: u16
} }
impl RxBuffer { impl RxBuffer {
@ -24,27 +24,6 @@ impl RxBuffer {
tail_addr: ERXTAIL_DEFAULT tail_addr: ERXTAIL_DEFAULT
} }
} }
pub fn set_start_addr(&mut self, addr: u16) {
self.start_addr = addr;
}
pub fn get_start_addr(& self) -> u16{
self.start_addr
}
pub fn set_next_addr(&mut self, addr: u16) {
self.next_addr = addr;
}
pub fn get_next_addr(& self) -> u16 {
self.next_addr
}
pub fn set_tail_addr(&mut self, addr: u16) {
self.tail_addr = addr;
}
pub fn get_tail_addr(& self) -> u16{
self.tail_addr
}
} }
/// Struct for RX Packet /// Struct for RX Packet

2
src/spi.rs
View File

@ -14,6 +14,7 @@ pub mod interfaces {
pub const SPI_CLOCK_FREQ: u32 = 14_000_000; pub const SPI_CLOCK_FREQ: u32 = 14_000_000;
} }
#[allow(dead_code)]
pub mod opcodes { pub mod opcodes {
/// 1-byte Instructions /// 1-byte Instructions
pub const SETETHRST: u8 = 0b1100_1010; pub const SETETHRST: u8 = 0b1100_1010;
@ -32,6 +33,7 @@ pub mod opcodes {
pub const WGPDATA: u8 = 0b0010_1010; // 8-bit opcode followed by data pub const WGPDATA: u8 = 0b0010_1010; // 8-bit opcode followed by data
} }
#[allow(dead_code)]
pub mod addrs { pub mod addrs {
/// SPI Register Mapping /// SPI Register Mapping
/// Note: PSP interface use different address mapping /// Note: PSP interface use different address mapping

27
src/tx.rs
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@ -3,10 +3,10 @@ use crate::RAW_FRAME_LENGTH_MAX;
/// Struct for TX Buffer on the hardware /// Struct for TX Buffer on the hardware
/// TODO: Should be a singleton /// TODO: Should be a singleton
pub struct TxBuffer { pub struct TxBuffer {
start_addr: u16, pub start_addr: u16,
// The following two fields are controlled by firmware // The following two fields are controlled by firmware
next_addr: u16, pub next_addr: u16,
tail_addr: u16 pub tail_addr: u16
} }
impl TxBuffer { impl TxBuffer {
@ -17,27 +17,6 @@ impl TxBuffer {
tail_addr: 0x0000 tail_addr: 0x0000
} }
} }
pub fn set_start_addr(&mut self, addr: u16) {
self.start_addr = addr;
}
pub fn get_start_addr(& self) -> u16{
self.start_addr
}
pub fn set_next_addr(&mut self, addr: u16) {
self.next_addr = addr;
}
pub fn get_next_addr(& self) -> u16 {
self.next_addr
}
pub fn set_tail_addr(&mut self, addr: u16) {
self.tail_addr = addr;
}
pub fn get_tail_addr(& self) -> u16{
self.tail_addr
}
} }
/// Struct for TX Packet /// Struct for TX Packet