SPI clock frequency selection is unclear #12

New Issue

harry · 2021-07-29T17:16:29+08:00

harry commented

2021-07-29 17:16:29 +08:00

I had an oversight in the STM32F407 examples where the selection of the SPI frequency (at max supported of 14MHz) lacks a correlation with the STM32 clock tree.

On STM32F407, the actual SPI clock frequency must be f_PCLK (frequency of the APB clock prescaled from SYSCLK) divided by 2, 4, 8, ..., or 256, which is determined by the BR[2:0] bits of the SPI_CR1 register. Luckily, the stm32f4xx_hal crate automatically choose the valid BR value by approximating (rounding down) the user-declared frequency value (see code). In the examples, the 14 MHz value is translated to 42/4 = 10.5 MHz.

On other MCUs, however, the supported crate might require that the user specify the frequency that matches the clock tree. Plus, on stm32f4xx_hal it is not immediately clear if the user-defined frequency will be rounded down or up, which might break the speed limit of ENC424J600.

Here are a few ways to improve:

In the STM32F407 examples, use 10.5 MHz instead of 14 MHz when initialising the SPI port. Add some comments to improve our communication with the user.
In README, add a note to clarify the maximum SPI clock frequency supported by ENC424J600, and that the SPI_CLOCK_FREQ const refers to this upper limit rather than the fixed requirement.
Completely throw away the SPI_CLOCK_FREQ const. Possibly add an assertion check on the user-defined value against the hardware limit.

I had an oversight in the STM32F407 examples where the selection of the SPI frequency (at max supported of 14MHz) lacks a correlation with the STM32 clock tree. On STM32F407, the actual SPI clock frequency must be f_PCLK (frequency of the APB clock prescaled from SYSCLK) divided by 2, 4, 8, ..., or 256, which is determined by the `BR[2:0]` bits of the `SPI_CR1` register. Luckily, the stm32f4xx_hal crate automatically choose the valid `BR` value by approximating (rounding down) the user-declared frequency value (see [code](https://github.com/stm32-rs/stm32f4xx-hal/blob/v0.8.3/src/spi.rs#L910-L920)). In the examples, the 14 MHz value is translated to 42/4 = 10.5 MHz. On other MCUs, however, the supported crate might require that the user specify the frequency that matches the clock tree. Plus, on stm32f4xx_hal it is not immediately clear if the user-defined frequency will be rounded down or up, which might break the speed limit of ENC424J600. Here are a few ways to improve: 1. In the STM32F407 examples, use 10.5 MHz instead of 14 MHz when initialising the SPI port. Add some comments to improve our communication with the user. 2. In README, add a note to clarify the maximum SPI clock frequency supported by ENC424J600, and that the `SPI_CLOCK_FREQ` const refers to this upper limit rather than the fixed requirement. 3. Completely throw away the `SPI_CLOCK_FREQ` const. Possibly add an assertion check on the user-defined value against the hardware limit.

harry self-assigned this 2021-07-29 17:37:37 +08:00

Sign in to join this conversation.

No Label

No Milestone

No project

No Assignees

1 Participants

Notifications

Due Date

The due date is invalid or out of range. Please use the format 'yyyy-mm-dd'.

No due date set.

Dependencies

No dependencies set.

Reference: renet/ENC424J600#12