renet
/
ENC424J600
10
1
Fork 1
Code Issues 3 Pull Requests 1 Projects Releases Wiki Activity

Compare commits

base: renet:master
Branches Tags
renet:master
renet:fix-spi-clk
renet:fix-visibility
renet:fix-spi
renet:fix-nal
renet:fix-cargo
occheung:feature/nal
occheung:smoltcp-bump
occheung:nal_support
occheung:feature/booster
occheung:master
..
compare: occheung:feature/nal
Branches Tags
occheung:feature/nal
occheung:smoltcp-bump
occheung:nal_support
occheung:feature/booster
occheung:master
renet:master
renet:fix-spi-clk
renet:fix-visibility
renet:fix-spi
renet:fix-nal
renet:fix-cargo

No commits in common. "master" and "feature/nal" have entirely different histories.
master ... feature/na

13 changed files with 727 additions and 583 deletions
Show Stats Expand all files Collapse all files

117
.github/workflows/ci.yml vendored
View File

@ -1,117 +0,0 @@
name: Continuous Integration
on:
push:
branches: [master]
pull_request:
branches: [master]
env:
CARGO_TERM_COLOR: always
jobs:
style:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- uses: actions-rs/toolchain@v1
with:
profile: minimal
toolchain: stable
override: true
components: rustfmt
- name: Style Check
uses: actions-rs/cargo@v1
with:
command: fmt
args: --all -- --check
clippy:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- uses: actions-rs/toolchain@v1
with:
profile: minimal
toolchain: stable
target: thumbv7em-none-eabihf
override: true
components: clippy
- name: Clippy Check
uses: actions-rs/cargo@v1
with:
command: clippy
args: --all-features
documentation:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- uses: actions-rs/toolchain@v1
with:
profile: minimal
toolchain: stable
target: thumbv7em-none-eabihf
override: true
- name: Cargo Doc
uses: actions-rs/cargo@v1
with:
command: doc
args: --all-features
audit:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- name: Cargo Audit
uses: actions-rs/audit-check@v1
with:
token: ${{ secrets.GITHUB_TOKEN }}
compile:
runs-on: ubuntu-latest
strategy:
matrix:
toolchain:
- stable
- beta
steps:
- uses: actions/checkout@v2
- name: Install Rust ${{ matrix.toolchain }}
uses: actions-rs/toolchain@v1
with:
toolchain: ${{ matrix.toolchain }}
target: thumbv7em-none-eabihf
override: true
- name: Cargo Check
uses: actions-rs/cargo@v1
with:
command: check
args: --verbose --all-features
- name: Cargo Build
uses: actions-rs/cargo@v1
with:
command: build
args: --all-features
- name: Cargo Build [Release]
uses: actions-rs/cargo@v1
with:
command: build
args: --release --all-features
- name: Cargo Build [Examples]
uses: actions-rs/cargo@v1
with:
command: build
args: --examples --all-features

39
Cargo.toml
View File

@ -1,9 +1,9 @@
[package]
categories = ["embedded", "no-std"]
name = "enc424j600"
description = "Embbeded Rust Ethernet driver for ENC424J600 Ethernet controller with SPI interface"
authors = ["Harry Ho <hh@m-labs.hk>", "Dip Cheung <dc@m-labs.hk>"]
version = "0.3.0"
description = "Embbeded Rust Ethernet driver for ENC424J600 Ethernet controller with SPI interface, compatible with STM32F4xx"
authors = ["Harry Ho <hh@m-labs.hk>"]
version = "0.2.0"
keywords = ["ethernet", "eth", "enc424j600", "stm32", "stm32f4xx"]
repository = "https://git.m-labs.hk/M-Labs/ENC424J600"
edition = "2018"
@ -13,30 +13,37 @@ license = "BSD-2-Clause"
volatile-register = "0.2"
aligned = "0.3"
embedded-hal = "0.2"
smoltcp = { version = "0.7.0", default-features = false, features = [ "socket-raw", "proto-ipv4",
"proto-ipv6", "socket-tcp", "ethernet"], optional = true }
cortex-m = {version = "0.5", optional = true }
smoltcp = { version = "0.7.0", default-features = false, features = ["proto-ipv4", "proto-ipv6", "socket-icmp", "socket-udp", "socket-tcp", "log", "verbose", "ethernet"], optional = true }
# Optional dependencies for building examples
[dev-dependencies]
stm32f4xx-hal = { version = "0.8", features = ["stm32f407", "rt"] }
cortex-m-rt = "0.6"
cortex-m-rtic = "0.5.3"
panic-itm = "0.4"
log = "0.4"
stm32f4xx-hal = { version = "0.8", optional = true }
cortex-m = { version = "0.5", optional = true }
cortex-m-rt = { version = "0.6", optional = true }
cortex-m-rtic = { version = "0.5.3", optional = true }
panic-itm = { version = "0.4", optional = true }
log = { version = "0.4", optional = true }
embedded-time = { version = "0.10.1", optional = true }
embedded-nal = { version = "0.1.0", optional = true }
heapless = { version = "0.5.6", optional = true }
[features]
smoltcp-phy = ["smoltcp"]
cortex-m-cpu = ["cortex-m"]
smoltcp-phy-all = [
"smoltcp/socket-raw", "smoltcp/socket-udp", "smoltcp/socket-tcp",
"smoltcp/proto-ipv4", "smoltcp/proto-ipv6"
]
# Example-based features
tx_stm32f407 = ["stm32f4xx-hal/stm32f407", "cortex-m", "cortex-m-rtic", "panic-itm", "log"]
tcp_stm32f407 = ["stm32f4xx-hal/stm32f407", "cortex-m", "cortex-m-rt", "cortex-m-rtic", "smoltcp-phy-all", "smoltcp/log", "panic-itm", "log"]
nal = [ "embedded-time", "embedded-nal", "smoltcp-phy", "heapless" ]
default = []
[[example]]
name = "tx_stm32f407"
required-features = ["smoltcp", "cortex-m-cpu"]
required-features = ["tx_stm32f407"]
[[example]]
name = "tcp_stm32f407"
required-features = ["smoltcp", "cortex-m-cpu"]
required-features = ["tcp_stm32f407"]
[profile.release]
codegen-units = 1

141
examples/tcp_stm32f407.rs
View File

@ -2,31 +2,43 @@
#![no_main]
extern crate panic_itm;
use cortex_m::{iprint, iprintln};
use cortex_m::{iprintln, iprint};
use embedded_hal::{blocking::delay::DelayMs, digital::v2::OutputPin};
use enc424j600::smoltcp_phy;
use stm32f4xx_hal::{
delay::Delay, gpio::GpioExt, rcc::RccExt, spi::Spi, stm32::ITM, time::Hertz, time::U32Ext,
use embedded_hal::{
digital::v2::OutputPin,
blocking::delay::DelayMs
};
use stm32f4xx_hal::{
rcc::RccExt,
gpio::GpioExt,
time::U32Ext,
stm32::ITM,
delay::Delay,
spi::Spi,
time::Hertz
};
use enc424j600;
use enc424j600::{smoltcp_phy, EthController};
use core::fmt::Write;
use core::str;
use smoltcp::iface::{EthernetInterface, EthernetInterfaceBuilder, NeighborCache};
use smoltcp::wire::{
EthernetAddress, IpAddress, IpCidr, Ipv6Cidr
};
use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder, EthernetInterface};
use smoltcp::socket::{SocketSet, TcpSocket, TcpSocketBuffer};
use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr, Ipv6Cidr};
use core::str;
use core::fmt::Write;
/// Timer
use core::cell::RefCell;
use cortex_m::interrupt::Mutex;
use cortex_m_rt::exception;
use smoltcp::time::Instant;
use stm32f4xx_hal::{
rcc::Clocks,
stm32::SYST,
time::MilliSeconds,
timer::{Event as TimerEvent, Timer},
timer::{Timer, Event as TimerEvent},
stm32::SYST
};
use smoltcp::time::Instant;
/// Rate in Hz
const TIMER_RATE: u32 = 20;
/// Interval duration in milliseconds
@ -44,34 +56,32 @@ fn timer_setup(syst: SYST, clocks: Clocks) {
#[exception]
fn SysTick() {
cortex_m::interrupt::free(|cs| {
*TIMER_MS.borrow(cs).borrow_mut() += TIMER_DELTA;
*TIMER_MS.borrow(cs)
.borrow_mut() += TIMER_DELTA;
});
}
/// Obtain current time in milliseconds
pub fn timer_now() -> MilliSeconds {
let ms = cortex_m::interrupt::free(|cs| *TIMER_MS.borrow(cs).borrow());
let ms = cortex_m::interrupt::free(|cs| {
*TIMER_MS.borrow(cs)
.borrow()
});
ms.ms()
}
///
use stm32f4xx_hal::{
gpio::{
gpioa::{PA4, PA5, PA6, PA7},
Alternate, Output, PushPull, AF5,
},
stm32::SPI1,
gpio::{
gpioa::{PA5, PA6, PA7, PA4},
Alternate, AF5, Output, PushPull
}
};
type SpiEth = enc424j600::Enc424j600<
Spi<
SPI1,
(
PA5<Alternate<AF5>>,
PA6<Alternate<AF5>>,
PA7<Alternate<AF5>>,
),
>,
type BoosterSpiEth = enc424j600::SpiEth<
Spi<SPI1, (PA5<Alternate<AF5>>, PA6<Alternate<AF5>>, PA7<Alternate<AF5>>)>,
PA4<Output<PushPull>>,
fn(u32) -> ()
>;
pub struct NetStorage {
@ -81,15 +91,19 @@ pub struct NetStorage {
static mut NET_STORE: NetStorage = NetStorage {
// Placeholder for the real IP address, which is initialized at runtime.
ip_addrs: [IpCidr::Ipv6(Ipv6Cidr::SOLICITED_NODE_PREFIX)],
ip_addrs: [IpCidr::Ipv6(
Ipv6Cidr::SOLICITED_NODE_PREFIX,
)],
neighbor_cache: [None; 8],
};
#[rtic::app(device = stm32f4xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
const APP: () = {
struct Resources {
eth_iface: EthernetInterface<'static, smoltcp_phy::SmoltcpDevice<SpiEth>>,
itm: ITM,
eth_iface: EthernetInterface<
'static,
smoltcp_phy::SmoltcpDevice<BoosterSpiEth>>,
itm: ITM
}
#[init()]
@ -101,10 +115,7 @@ const APP: () = {
c.core.DWT.enable_cycle_counter();
c.core.DCB.enable_trace();
let clocks = c
.device
.RCC
.constrain()
let clocks = c.device.RCC.constrain()
.cfgr
.sysclk(168.mhz())
.hclk(168.mhz())
@ -117,7 +128,8 @@ const APP: () = {
let mut itm = c.core.ITM;
let stim0 = &mut itm.stim[0];
iprintln!(stim0, "Eth TCP Server on STM32-F407 via NIC100/ENC424J600");
iprintln!(stim0,
"Eth TCP Server on STM32-F407 via NIC100/ENC424J600");
// NIC100 / ENC424J600 Set-up
let spi1 = c.device.SPI1;
@ -137,18 +149,19 @@ const APP: () = {
let eth_iface = {
let mut spi_eth = {
let spi_eth_port = Spi::spi1(
spi1,
(spi1_sck, spi1_miso, spi1_mosi),
spi1, (spi1_sck, spi1_miso, spi1_mosi),
enc424j600::spi::interfaces::SPI_MODE,
Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ),
clocks,
);
clocks);
SpiEth::new(spi_eth_port, spi1_nss).cpu_freq_mhz(168)
let delay_ns_fp: fn(u32) -> () = |time_ns| {
cortex_m::asm::delay((time_ns*21)/125 + 1)
};
enc424j600::SpiEth::new(spi_eth_port, spi1_nss, delay_ns_fp)
};
// Init controller
match spi_eth.reset(&mut delay) {
match spi_eth.init_dev() {
Ok(_) => {
iprintln!(stim0, "Initializing Ethernet...")
}
@ -159,14 +172,14 @@ const APP: () = {
// Read MAC
let mut eth_mac_addr: [u8; 6] = [0; 6];
spi_eth.read_mac_addr(&mut eth_mac_addr);
spi_eth.read_from_mac(&mut eth_mac_addr);
for i in 0..6 {
let byte = eth_mac_addr[i];
match i {
0 => iprint!(stim0, "MAC Address = {:02x}-", byte),
1..=4 => iprint!(stim0, "{:02x}-", byte),
5 => iprint!(stim0, "{:02x}\n", byte),
_ => (),
_ => ()
};
}
@ -199,7 +212,10 @@ const APP: () = {
timer_setup(delay.free(), clocks);
iprintln!(stim0, "Timer initialized");
init::LateResources { eth_iface, itm }
init::LateResources {
eth_iface,
itm
}
}
#[idle(resources=[eth_iface, itm])]
@ -229,11 +245,8 @@ const APP: () = {
let greet_handle = socket_set.add(greet_socket);
{
let store = unsafe { &mut NET_STORE };
iprintln!(
stim0,
"TCP sockets will listen at {}",
store.ip_addrs[0].address()
);
iprintln!(stim0,
"TCP sockets will listen at {}", store.ip_addrs[0].address());
}
// Copied / modified from:
@ -245,7 +258,8 @@ const APP: () = {
let now = timer_now().0;
let instant = Instant::from_millis(now as i64);
match iface.poll(&mut socket_set, instant) {
Ok(_) => {}
Ok(_) => {
},
Err(e) => {
iprintln!(stim0, "[{}] Poll error: {:?}", instant, e)
}
@ -254,40 +268,33 @@ const APP: () = {
{
let mut socket = socket_set.get::<TcpSocket>(echo_handle);
if !socket.is_open() {
iprintln!(
stim0,
"[{}] Listening to port 1234 for echoing, time-out in 10s",
instant
);
iprintln!(stim0,
"[{}] Listening to port 1234 for echoing, time-out in 10s", instant);
socket.listen(1234).unwrap();
socket.set_timeout(Some(smoltcp::time::Duration::from_millis(10000)));
}
if socket.can_recv() {
iprintln!(
stim0,
"[{}] Received packet: {:?}",
instant,
socket.recv(|buffer| { (buffer.len(), str::from_utf8(buffer).unwrap()) })
);
iprintln!(stim0,
"[{}] Received packet: {:?}", instant, socket.recv(|buffer| {
(buffer.len(), str::from_utf8(buffer).unwrap())
}));
}
}
// Control the "greeting" socket (:4321)
{
let mut socket = socket_set.get::<TcpSocket>(greet_handle);
if !socket.is_open() {
iprintln!(
stim0,
iprintln!(stim0,
"[{}] Listening to port 4321 for greeting, \
please connect to the port",
instant
);
please connect to the port", instant);
socket.listen(4321).unwrap();
}
if socket.can_send() {
let greeting = "Welcome to the server demo for STM32-F407!";
write!(socket, "{}\n", greeting).unwrap();
iprintln!(stim0, "[{}] Greeting sent, socket closed", instant);
iprintln!(stim0,
"[{}] Greeting sent, socket closed", instant);
socket.close();
}
}

92
examples/tx_stm32f407.rs
View File

@ -2,38 +2,41 @@
#![no_main]
extern crate panic_itm;
use cortex_m::{iprint, iprintln};
use cortex_m::{iprintln, iprint};
use embedded_hal::{blocking::delay::DelayMs, digital::v2::OutputPin};
use enc424j600::EthPhy;
use stm32f4xx_hal::{
delay::Delay, gpio::GpioExt, rcc::RccExt, spi::Spi, stm32::ITM, time::Hertz, time::U32Ext,
use embedded_hal::{
digital::v2::OutputPin,
blocking::delay::DelayMs
};
use stm32f4xx_hal::{
rcc::RccExt,
gpio::GpioExt,
time::U32Ext,
stm32::ITM,
delay::Delay,
spi::Spi,
time::Hertz
};
use enc424j600;
use enc424j600::EthController;
///
use stm32f4xx_hal::{
gpio::{
gpioa::{PA4, PA5, PA6, PA7},
Alternate, Output, PushPull, AF5,
},
stm32::SPI1,
gpio::{
gpioa::{PA5, PA6, PA7, PA4},
Alternate, AF5, Output, PushPull
},
};
type SpiEth = enc424j600::Enc424j600<
Spi<
SPI1,
(
PA5<Alternate<AF5>>,
PA6<Alternate<AF5>>,
PA7<Alternate<AF5>>,
),
>,
type BoosterSpiEth = enc424j600::SpiEth<
Spi<SPI1, (PA5<Alternate<AF5>>, PA6<Alternate<AF5>>, PA7<Alternate<AF5>>)>,
PA4<Output<PushPull>>,
>;
fn(u32)>;
#[rtic::app(device = stm32f4xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
const APP: () = {
struct Resources {
spi_eth: SpiEth,
spi_eth: BoosterSpiEth,
delay: Delay,
itm: ITM,
}
@ -43,10 +46,7 @@ const APP: () = {
c.core.SCB.enable_icache();
c.core.SCB.enable_dcache(&mut c.core.CPUID);
let clocks = c
.device
.RCC
.constrain()
let clocks = c.device.RCC.constrain()
.cfgr
.sysclk(168.mhz())
.hclk(168.mhz())
@ -60,7 +60,8 @@ const APP: () = {
// Init ITM
let mut itm = c.core.ITM;
let stim0 = &mut itm.stim[0];
iprintln!(stim0, "Eth TX Pinging on STM32-F407 via NIC100/ENC424J600");
iprintln!(stim0,
"Eth TX Pinging on STM32-F407 via NIC100/ENC424J600");
// NIC100 / ENC424J600 Set-up
let spi1 = c.device.SPI1;
@ -78,18 +79,19 @@ const APP: () = {
// Create SPI1 for HAL
let mut spi_eth = {
let spi_eth_port = Spi::spi1(
spi1,
(spi1_sck, spi1_miso, spi1_mosi),
spi1, (spi1_sck, spi1_miso, spi1_mosi),
enc424j600::spi::interfaces::SPI_MODE,
Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ),
clocks,
);
clocks);
SpiEth::new(spi_eth_port, spi1_nss).cpu_freq_mhz(168)
let delay_ns: fn(u32) -> () = |time_ns| {
cortex_m::asm::delay((time_ns*21)/125 + 1)
};
enc424j600::SpiEth::new(spi_eth_port, spi1_nss, delay_ns)
};
// Init
match spi_eth.reset(&mut delay) {
match spi_eth.init_dev() {
Ok(_) => {
iprintln!(stim0, "Initializing Ethernet...")
}
@ -100,14 +102,14 @@ const APP: () = {
// Read MAC
let mut eth_mac_addr: [u8; 6] = [0; 6];
spi_eth.read_mac_addr(&mut eth_mac_addr);
spi_eth.read_from_mac(&mut eth_mac_addr);
for i in 0..6 {
let byte = eth_mac_addr[i];
match i {
0 => iprint!(stim0, "MAC Address = {:02x}-", byte),
1..=4 => iprint!(stim0, "{:02x}-", byte),
5 => iprint!(stim0, "{:02x}\n", byte),
_ => (),
_ => ()
};
}
@ -128,20 +130,20 @@ const APP: () = {
let stim0 = &mut c.resources.itm.stim[0];
// Testing Eth TX
let eth_tx_dat: [u8; 64] = [
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x08, 0x60, 0x6e, 0x44, 0x42, 0x95, 0x08, 0x06,
0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01, 0x08, 0x60, 0x6e, 0x44, 0x42, 0x95,
0xc0, 0xa8, 0x01, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xa8, 0x01, 0xe7,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x69, 0xd0, 0x85, 0x9f,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x08, 0x60,
0x6e, 0x44, 0x42, 0x95, 0x08, 0x06, 0x00, 0x01,
0x08, 0x00, 0x06, 0x04, 0x00, 0x01, 0x08, 0x60,
0x6e, 0x44, 0x42, 0x95, 0xc0, 0xa8, 0x01, 0x64,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xa8,
0x01, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x69, 0xd0, 0x85, 0x9f
];
loop {
let mut eth_tx_packet = enc424j600::tx::TxPacket::new();
eth_tx_packet.update_frame(&eth_tx_dat, 64);
iprint!(
stim0,
"Sending packet (len={:}): ",
eth_tx_packet.get_frame_length()
);
iprint!(stim0,
"Sending packet (len={:}): ", eth_tx_packet.get_frame_length());
for i in 0..20 {
let byte = eth_tx_packet.get_frame_byte(i);
match i {
@ -152,10 +154,10 @@ const APP: () = {
13..=14 | 16..=18 => iprint!(stim0, "{:02x}", byte),
5 | 11 | 15 => iprint!(stim0, "{:02x} ", byte),
19 => iprint!(stim0, "{:02x} ...\n", byte),
_ => (),
_ => ()
};
}
c.resources.spi_eth.send_packet(&eth_tx_packet);
c.resources.spi_eth.send_raw_packet(&eth_tx_packet);
iprintln!(stim0, "Packet sent");
c.resources.delay.delay_ms(100_u32);
}

21
nix/itm-tools.nix Normal file
View File

@ -0,0 +1,21 @@
{ stdenv, fetchFromGitHub, rustPlatform, pkg-config }:
rustPlatform.buildRustPackage rec {
version = "2019-11-15";
pname = "itm-tools";
src = fetchFromGitHub {
owner = "japaric";
repo = "itm-tools";
rev = "e94155e44019d893ac8e6dab51cc282d344ab700";
sha256 = "19xkjym0i7y52cfhvis49c59nzvgw4906cd8bkz8ka38mbgfqgiy";
};
cargoPatches = [ ./itm-tools-cargo-lock.patch ];
cargoSha256 = "0is702s14pgvd5i2m8aaw3zcsshqrwj97mjgg3wikbc627pagzg7";
nativeBuildInputs = [ pkg-config ];
doCheck = false;
}

2
nix/rustPlatform.nix
View File

@ -10,7 +10,7 @@ let
];
rustChannel =
lib.rustLib.fromManifestFile rustManifest {
inherit stdenv lib fetchurl patchelf;
inherit stdenv fetchurl patchelf;
};
rust =
rustChannel.rust.override {

4
shell.nix
View File

@ -8,6 +8,8 @@ with pkgs;
let
rustPlatform = callPackage ./nix/rustPlatform.nix {};
itm-tools = callPackage ./nix/itm-tools.nix { inherit rustPlatform; };
runHelp = writeShellScriptBin "run-help" ''
echo "[Common Tools]"
echo " run-openocd-f4x"
@ -101,7 +103,7 @@ in
stdenv.mkDerivation {
name = "enc424j600-stm32-env";
buildInputs = with rustPlatform.rust; [
rustc cargo pkgs.gdb pkgs.openocd pkgs.tmux pkgs.itm-tools
rustc cargo pkgs.gdb pkgs.openocd pkgs.tmux itm-tools
runHelp runTmuxEnv killTmuxEnv
runOpenOcdF4x runItmDemuxFollow
exTxStm32f407 exTcpStm32f407

243
src/lib.rs
View File

@ -2,175 +2,137 @@
pub mod spi;
use embedded_hal::{
blocking::{delay::DelayUs, spi::Transfer},
blocking::{
spi::Transfer,
},
digital::v2::OutputPin,
};
pub mod rx;
pub mod tx;
#[cfg(feature = "smoltcp")]
#[cfg(feature="smoltcp")]
pub mod smoltcp_phy;
#[cfg(feature="nal")]
pub mod nal;
/// Max raw frame array size
pub const RAW_FRAME_LENGTH_MAX: usize = 1518;
/// Trait representing PHY layer of ENC424J600
pub trait EthPhy {
fn recv_packet(&mut self, is_poll: bool) -> Result<rx::RxPacket, Error>;
fn send_packet(&mut self, packet: &tx::TxPacket) -> Result<(), Error>;
pub trait EthController {
fn init_dev(&mut self) -> Result<(), EthControllerError>;
fn init_rxbuf(&mut self) -> Result<(), EthControllerError>;
fn init_txbuf(&mut self) -> Result<(), EthControllerError>;
fn receive_next(&mut self, is_poll: bool) -> Result<rx::RxPacket, EthControllerError>;
fn send_raw_packet(&mut self, packet: &tx::TxPacket) -> Result<(), EthControllerError>;
fn set_promiscuous(&mut self) -> Result<(), EthControllerError>;
fn read_from_mac(&mut self, mac: &mut [u8]) -> Result<(), EthControllerError>;
fn write_mac_address(&mut self, mac: &[u8]) -> Result<(), EthControllerError>;
}
/// TODO: Improve these error types
#[derive(Debug)]
pub enum Error {
pub enum EthControllerError {
SpiPortError,
RegisterError,
GeneralError,
// TODO: Better name?
NoRxPacketError,
NoRxPacketError
}
impl From<spi::Error> for Error {
fn from(_: spi::Error) -> Error {
Error::SpiPortError
impl From<spi::SpiPortError> for EthControllerError {
fn from(_: spi::SpiPortError) -> EthControllerError {
EthControllerError::SpiPortError
}
}
/// ENC424J600 controller in SPI mode
pub struct Enc424j600<SPI: Transfer<u8>, NSS: OutputPin> {
spi_port: spi::SpiPort<SPI, NSS>,
/// Ethernet controller using SPI interface
pub struct SpiEth<SPI: Transfer<u8>,
NSS: OutputPin,
F: FnMut(u32) -> ()> {
spi_port: spi::SpiPort<SPI, NSS, F>,
rx_buf: rx::RxBuffer,
tx_buf: tx::TxBuffer,
tx_buf: tx::TxBuffer
}
impl<SPI: Transfer<u8>, NSS: OutputPin> Enc424j600<SPI, NSS> {
pub fn new(spi: SPI, nss: NSS) -> Self {
Enc424j600 {
spi_port: spi::SpiPort::new(spi, nss),
impl <SPI: Transfer<u8>,
NSS: OutputPin,
F: FnMut(u32) -> ()> SpiEth<SPI, NSS, F> {
pub fn new(spi: SPI, nss: NSS, delay_ns: F) -> Self {
SpiEth {
spi_port: spi::SpiPort::new(spi, nss, delay_ns),
rx_buf: rx::RxBuffer::new(),
tx_buf: tx::TxBuffer::new(),
tx_buf: tx::TxBuffer::new()
}
}
}
#[cfg(feature = "cortex-m-cpu")]
pub fn cpu_freq_mhz(mut self, freq: u32) -> Self {
self.spi_port = self.spi_port.cpu_freq_mhz(freq);
self
}
pub fn init(&mut self, delay: &mut impl DelayUs<u16>) -> Result<(), Error> {
self.reset(delay)?;
self.init_rxbuf()?;
self.init_txbuf()?;
Ok(())
}
pub fn reset(&mut self, delay: &mut impl DelayUs<u16>) -> Result<(), Error> {
impl <SPI: Transfer<u8>,
NSS: OutputPin,
F: FnMut(u32) -> ()> EthController for SpiEth<SPI, NSS, F> {
fn init_dev(&mut self) -> Result<(), EthControllerError> {
// Write 0x1234 to EUDAST
self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?;
// Verify that EUDAST is 0x1234
let mut eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
if eudast != 0x1234 {
return Err(Error::RegisterError);
return Err(EthControllerError::GeneralError)
}
// Poll CLKRDY (ESTAT<12>) to check if it is set
loop {
let estat = self.spi_port.read_reg_16b(spi::addrs::ESTAT)?;
if estat & 0x1000 == 0x1000 {
break;
}
if estat & 0x1000 == 0x1000 { break }
}
// Issue system reset - set ETHRST (ECON2<4>) to 1
self.spi_port.send_opcode(spi::opcodes::SETETHRST)?;
delay.delay_us(25);
// Set ETHRST (ECON2<4>) to 1
let econ2 = self.spi_port.read_reg_8b(spi::addrs::ECON2)?;
self.spi_port.write_reg_8b(spi::addrs::ECON2, 0x10 | (econ2 & 0b11101111))?;
self.spi_port.delay_us(25);
// Verify that EUDAST is 0x0000
eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
if eudast != 0x0000 {
return Err(Error::RegisterError);
return Err(EthControllerError::GeneralError)
}
delay.delay_us(256);
self.spi_port.delay_us(256);
Ok(())
}
pub fn init_rxbuf(&mut self) -> Result<(), Error> {
fn init_rxbuf(&mut self) -> Result<(), EthControllerError> {
// Set ERXST pointer
self.spi_port
.write_reg_16b(spi::addrs::ERXST, self.rx_buf.get_start_addr())?;
self.spi_port.write_reg_16b(spi::addrs::ERXST, self.rx_buf.get_wrap_addr())?;
// Set ERXTAIL pointer
self.spi_port
.write_reg_16b(spi::addrs::ERXTAIL, self.rx_buf.get_tail_addr())?;
self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, self.rx_buf.get_tail_addr())?;
// Set MAMXFL to maximum number of bytes in each accepted packet
self.spi_port
.write_reg_16b(spi::addrs::MAMXFL, RAW_FRAME_LENGTH_MAX as u16)?;
// Enable RX - set RXEN (ECON1<0>) to 1
self.spi_port.send_opcode(spi::opcodes::ENABLERX)?;
self.spi_port.write_reg_16b(spi::addrs::MAMXFL, RAW_FRAME_LENGTH_MAX as u16)?;
// Enable RXEN (ECON1<0>)
let econ1 = self.spi_port.read_reg_16b(spi::addrs::ECON1)?;
self.spi_port.write_reg_16b(spi::addrs::ECON1, 0x1 | (econ1 & 0xfffe))?;
Ok(())
}
pub fn init_txbuf(&mut self) -> Result<(), Error> {
fn init_txbuf(&mut self) -> Result<(), EthControllerError> {
// Set EGPWRPT pointer
self.spi_port.write_reg_16b(spi::addrs::EGPWRPT, 0x0000)?;
Ok(())
}
/// Set controller to Promiscuous Mode
pub fn set_promiscuous(&mut self) -> Result<(), Error> {
// From Section 10.12, ENC424J600 Data Sheet:
// "To accept all incoming frames regardless of content (Promiscuous mode),
// set the CRCEN, RUNTEN, UCEN, NOTMEEN and MCEN bits."
let erxfcon_lo = self.spi_port.read_reg_8b(spi::addrs::ERXFCON)?;
self.spi_port.write_reg_8b(
spi::addrs::ERXFCON,
0b0101_1110 | (erxfcon_lo & 0b1010_0001),
)?;
Ok(())
}
/// Read MAC to [u8; 6]
pub fn read_mac_addr(&mut self, mac: &mut [u8]) -> Result<(), Error> {
mac[0] = self.spi_port.read_reg_8b(spi::addrs::MAADR1)?;
mac[1] = self.spi_port.read_reg_8b(spi::addrs::MAADR1 + 1)?;
mac[2] = self.spi_port.read_reg_8b(spi::addrs::MAADR2)?;
mac[3] = self.spi_port.read_reg_8b(spi::addrs::MAADR2 + 1)?;
mac[4] = self.spi_port.read_reg_8b(spi::addrs::MAADR3)?;
mac[5] = self.spi_port.read_reg_8b(spi::addrs::MAADR3 + 1)?;
Ok(())
}
pub fn write_mac_addr(&mut self, mac: &[u8]) -> Result<(), Error> {
self.spi_port.write_reg_8b(spi::addrs::MAADR1, mac[0])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR1 + 1, mac[1])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR2, mac[2])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR2 + 1, mac[3])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR3, mac[4])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR3 + 1, mac[5])?;
Ok(())
}
}
impl<SPI: Transfer<u8>, NSS: OutputPin> EthPhy for Enc424j600<SPI, NSS> {
/// Receive the next packet and return it
/// Set is_poll to true for returning until PKTIF is set;
/// Set is_poll to false for returning Err when PKTIF is not set
fn recv_packet(&mut self, is_poll: bool) -> Result<rx::RxPacket, Error> {
fn receive_next(&mut self, is_poll: bool) -> Result<rx::RxPacket, EthControllerError> {
// Poll PKTIF (EIR<4>) to check if it is set
loop {
let eir = self.spi_port.read_reg_16b(spi::addrs::EIR)?;
if eir & 0x40 == 0x40 {
break;
}
if eir & 0x40 == 0x40 { break }
if !is_poll {
return Err(Error::NoRxPacketError);
return Err(EthControllerError::NoRxPacketError)
}
}
// Set ERXRDPT pointer to next_addr
self.spi_port
.write_reg_16b(spi::addrs::ERXRDPT, self.rx_buf.get_next_addr())?;
self.spi_port.write_reg_16b(spi::addrs::ERXRDPT, self.rx_buf.get_next_addr())?;
// Read 2 bytes to update next_addr
let mut next_addr_buf = [0; 3];
self.spi_port.read_rxdat(&mut next_addr_buf, 2)?;
self.rx_buf
.set_next_addr((next_addr_buf[1] as u16) | ((next_addr_buf[2] as u16) << 8));
self.rx_buf.set_next_addr((next_addr_buf[1] as u16) | ((next_addr_buf[2] as u16) << 8));
// Read 6 bytes to update rsv
let mut rsv_buf = [0; 7];
self.spi_port.read_rxdat(&mut rsv_buf, 6)?;
@ -182,61 +144,78 @@ impl<SPI: Transfer<u8>, NSS: OutputPin> EthPhy for Enc424j600<SPI, NSS> {
rx_packet.update_frame_length();
// Read frame bytes
let mut frame_buf = [0; RAW_FRAME_LENGTH_MAX];
self.spi_port
.read_rxdat(&mut frame_buf, rx_packet.get_frame_length())?;
self.spi_port.read_rxdat(&mut frame_buf, rx_packet.get_frame_length())?;
rx_packet.copy_frame_from(&frame_buf[1..]);
// Set ERXTAIL pointer to (next_addr - 2)
// * Assume head, tail, next and wrap addresses are word-aligned (even)
// - If next_addr is at least (start_addr+2), then set tail pointer to the word right before next_addr
if self.rx_buf.get_next_addr() > self.rx_buf.get_start_addr() {
self.spi_port
.write_reg_16b(spi::addrs::ERXTAIL, self.rx_buf.get_next_addr() - 2)?;
// - Otherwise, next_addr will wrap, so set tail pointer to the last word address of RX buffer
if self.rx_buf.get_next_addr() > rx::ERXST_DEFAULT {
self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, self.rx_buf.get_next_addr() - 2)?;
} else {
self.spi_port
.write_reg_16b(spi::addrs::ERXTAIL, rx::RX_MAX_ADDRESS - 1)?;
self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, rx::RX_MAX_ADDRESS - 1)?;
}
// Decrement PKTCNT - set PKTDEC (ECON1<8>)
self.spi_port.send_opcode(spi::opcodes::SETPKTDEC)?;
// Set PKTDEC (ECON1<88>) to decrement PKTCNT
let econ1_hi = self.spi_port.read_reg_8b(spi::addrs::ECON1 + 1)?;
self.spi_port.write_reg_8b(spi::addrs::ECON1 + 1, 0x01 | (econ1_hi & 0xfe))?;
// Return the RxPacket
Ok(rx_packet)
}
/// Send an established packet
fn send_packet(&mut self, packet: &tx::TxPacket) -> Result<(), Error> {
fn send_raw_packet(&mut self, packet: &tx::TxPacket) -> Result<(), EthControllerError> {
// Set EGPWRPT pointer to next_addr
self.spi_port
.write_reg_16b(spi::addrs::EGPWRPT, self.tx_buf.get_next_addr())?;
self.spi_port.write_reg_16b(spi::addrs::EGPWRPT, self.tx_buf.get_next_addr())?;
// Copy packet data to SRAM Buffer
// 1-byte Opcode is included
let mut txdat_buf: [u8; RAW_FRAME_LENGTH_MAX + 1] = [0; RAW_FRAME_LENGTH_MAX + 1];
packet.write_frame_to(&mut txdat_buf[1..]);
self.spi_port
.write_txdat(&mut txdat_buf, packet.get_frame_length())?;
self.spi_port.write_txdat(&mut txdat_buf, packet.get_frame_length())?;
// Set ETXST to packet start address
self.spi_port
.write_reg_16b(spi::addrs::ETXST, self.tx_buf.get_next_addr())?;
self.spi_port.write_reg_16b(spi::addrs::ETXST, self.tx_buf.get_next_addr())?;
// Set ETXLEN to packet length
self.spi_port
.write_reg_16b(spi::addrs::ETXLEN, packet.get_frame_length() as u16)?;
// Send packet - set TXRTS (ECON1<1>) to start transmission
self.spi_port.send_opcode(spi::opcodes::SETTXRTS)?;
self.spi_port.write_reg_16b(spi::addrs::ETXLEN, packet.get_frame_length() as u16)?;
// Set TXRTS (ECON1<1>) to start transmission
let mut econ1_lo = self.spi_port.read_reg_8b(spi::addrs::ECON1)?;
self.spi_port.write_reg_8b(spi::addrs::ECON1, 0x02 | (econ1_lo & 0xfd))?;
// Poll TXRTS (ECON1<1>) to check if it is reset
loop {
let econ1_lo = self.spi_port.read_reg_8b(spi::addrs::ECON1)?;
if econ1_lo & 0x02 == 0 {
break;
}
econ1_lo = self.spi_port.read_reg_8b(spi::addrs::ECON1)?;
if econ1_lo & 0x02 == 0 { break }
}
// TODO: Read ETXSTAT to understand Ethernet transmission status
// (See: Register 9-2, ENC424J600 Data Sheet)
// Update TX buffer start address
// * Assume TX buffer consumes the entire general-purpose SRAM block
self.tx_buf.set_next_addr(
(self.tx_buf.get_next_addr() + packet.get_frame_length() as u16)
% self.rx_buf.get_start_addr()
- self.tx_buf.get_start_addr(),
);
self.tx_buf.set_next_addr((self.tx_buf.get_next_addr() + packet.get_frame_length() as u16) %
tx::GPBUFEN_DEFAULT);
Ok(())
}
/// Set controller to Promiscuous Mode
fn set_promiscuous(&mut self) -> Result<(), EthControllerError> {
// From Section 10.12, ENC424J600 Data Sheet:
// "To accept all incoming frames regardless of content (Promiscuous mode),
// set the CRCEN, RUNTEN, UCEN, NOTMEEN and MCEN bits."
let erxfcon_lo = self.spi_port.read_reg_8b(spi::addrs::ERXFCON)?;
self.spi_port.write_reg_8b(spi::addrs::ERXFCON, 0b0101_1110 | (erxfcon_lo & 0b1010_0001))?;
Ok(())
}
/// Read MAC to [u8; 6]
fn read_from_mac(&mut self, mac: &mut [u8]) -> Result<(), EthControllerError> {
mac[0] = self.spi_port.read_reg_8b(spi::addrs::MAADR1)?;
mac[1] = self.spi_port.read_reg_8b(spi::addrs::MAADR1 + 1)?;
mac[2] = self.spi_port.read_reg_8b(spi::addrs::MAADR2)?;
mac[3] = self.spi_port.read_reg_8b(spi::addrs::MAADR2 + 1)?;
mac[4] = self.spi_port.read_reg_8b(spi::addrs::MAADR3)?;
mac[5] = self.spi_port.read_reg_8b(spi::addrs::MAADR3 + 1)?;
Ok(())
}
fn write_mac_address(&mut self, mac: &[u8]) -> Result<(), EthControllerError> {
self.spi_port.write_reg_8b(spi::addrs::MAADR1, mac[0])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR1 + 1, mac[1])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR2, mac[2])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR2 + 1, mac[3])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR3, mac[4])?;
self.spi_port.write_reg_8b(spi::addrs::MAADR3 + 1, mac[5])?;
Ok(())
}
}

245
src/nal.rs Normal file
View File

@ -0,0 +1,245 @@
use core::cell::RefCell;
use core::convert::TryFrom;
use heapless::{consts, Vec};
use embedded_nal as nal;
use nal::nb;
use smoltcp as net;
use embedded_hal::{
blocking::spi::Transfer,
digital::v2::OutputPin
};
pub use embedded_time as time;
use time::duration::*;
#[derive(Debug)]
pub enum NetworkError {
NoSocket,
ConnectionFailure,
ReadFailure,
WriteFailure,
Unsupported,
TimeFault,
}
pub type NetworkInterface<SPI, NSS> = net::iface::EthernetInterface<
'static,
crate::smoltcp_phy::SmoltcpDevice<
crate::SpiEth<SPI, NSS, fn(u32)>
>,
>;
pub struct NetworkStack<'a, SPI, NSS, IntClock>
where
SPI: 'static + Transfer<u8>,
NSS: 'static + OutputPin,
IntClock: time::Clock<T = u32>,
{
network_interface: RefCell<NetworkInterface<SPI, NSS>>,
sockets: RefCell<net::socket::SocketSet<'a>>,
next_port: RefCell<u16>,
unused_handles: RefCell<Vec<net::socket::SocketHandle, consts::U16>>,
time_ms: RefCell<u32>,
last_update_instant: RefCell<Option<time::Instant<IntClock>>>,
clock: IntClock
}
impl<'a, SPI, NSS, IntClock> NetworkStack<'a, SPI, NSS, IntClock>
where
SPI: Transfer<u8>,
NSS: OutputPin,
IntClock: time::Clock<T = u32>,
{
pub fn new(interface: NetworkInterface<SPI, NSS>, sockets: net::socket::SocketSet<'a>, clock: IntClock) -> Self {
let mut unused_handles: Vec<net::socket::SocketHandle, consts::U16> = Vec::new();
for socket in sockets.iter() {
unused_handles.push(socket.handle()).unwrap();
}
NetworkStack {
network_interface: RefCell::new(interface),
sockets: RefCell::new(sockets),
next_port: RefCell::new(49152),
unused_handles: RefCell::new(unused_handles),
time_ms: RefCell::new(0),
last_update_instant: RefCell::new(None),
clock,
}
}
// Include auto_time_update to allow Instant::now() to not be called
// Instant::now() is not safe to call in `init()` context
pub fn update(&self, auto_time_update: bool) -> Result<bool, NetworkError> {
if auto_time_update {
// Check if it is the first time the stack has updated the time itself
let now = match *self.last_update_instant.borrow() {
// If it is the first time, do not advance time
// Simply store the current instant to initiate time updating
None => self.clock.try_now().map_err(|_| NetworkError::TimeFault)?,
// If it was updated before, advance time and update last_update_instant
Some(instant) => {
// Calculate elapsed time
let now = self.clock.try_now().map_err(|_| NetworkError::TimeFault)?;
let duration = now.checked_duration_since(&instant).ok_or(NetworkError::TimeFault)?;
let duration_ms = time::duration::Milliseconds::<u32>::try_from(duration).map_err(|_| NetworkError::TimeFault)?;
// Adjust duration into ms (note: decimal point truncated)
self.advance_time(*duration_ms.integer());
now
}
};
self.last_update_instant.replace(Some(now));
}
match self.network_interface.borrow_mut().poll(
&mut self.sockets.borrow_mut(),
net::time::Instant::from_millis(*self.time_ms.borrow() as i64),
) {
Ok(changed) => Ok(!changed),
Err(_e) => {
Ok(true)
}
}
}
pub fn advance_time(&self, duration: u32) {
let time = self.time_ms.try_borrow().unwrap().wrapping_add(duration);
self.time_ms.replace(time);
}
fn get_ephemeral_port(&self) -> u16 {
// Get the next ephemeral port
let current_port = self.next_port.borrow().clone();
let (next, wrap) = self.next_port.borrow().overflowing_add(1);
*self.next_port.borrow_mut() = if wrap { 49152 } else { next };
return current_port;
}
}
impl<'a, SPI, NSS, IntClock> nal::TcpStack for NetworkStack<'a, SPI, NSS, IntClock>
where
SPI: Transfer<u8>,
NSS: OutputPin,
IntClock: time::Clock<T = u32>,
{
type TcpSocket = net::socket::SocketHandle;
type Error = NetworkError;
fn open(&self, _mode: nal::Mode) -> Result<Self::TcpSocket, Self::Error> {
match self.unused_handles.borrow_mut().pop() {
Some(handle) => {
// Abort any active connections on the handle.
let mut sockets = self.sockets.borrow_mut();
let internal_socket: &mut net::socket::TcpSocket = &mut *sockets.get(handle);
internal_socket.abort();
Ok(handle)
}
None => Err(NetworkError::NoSocket),
}
}
// Ideally connect is only to be performed in `init()` of `main.rs`
// Calling `Instant::now()` of `rtic::cyccnt` would face correctness issue during `init()`
fn connect(
&self,
socket: Self::TcpSocket,
remote: nal::SocketAddr,
) -> Result<Self::TcpSocket, Self::Error> {
let address = {
let mut sockets = self.sockets.borrow_mut();
let internal_socket: &mut net::socket::TcpSocket = &mut *sockets.get(socket);
// If we're already in the process of connecting, ignore the request silently.
if internal_socket.is_open() {
return Ok(socket);
}
match remote.ip() {
nal::IpAddr::V4(addr) => {
let address =
net::wire::Ipv4Address::from_bytes(&addr.octets()[..]);
internal_socket
.connect((address, remote.port()), self.get_ephemeral_port())
.map_err(|_| NetworkError::ConnectionFailure)?;
net::wire::IpAddress::Ipv4(address)
}
nal::IpAddr::V6(addr) => {
let address = net::wire::Ipv6Address::from_parts(&addr.segments()[..]);
internal_socket.connect((address, remote.port()), self.get_ephemeral_port())
.map_err(|_| NetworkError::ConnectionFailure)?;
net::wire::IpAddress::Ipv6(address)
}
}
};
// Blocking connect
loop {
match self.is_connected(&socket) {
Ok(true) => break,
_ => {
let mut sockets = self.sockets.borrow_mut();
let internal_socket: &mut net::socket::TcpSocket = &mut *sockets.get(socket);
// If the connect got ACK->RST, it will end up in Closed TCP state
// Perform reconnection in this case
if internal_socket.state() == net::socket::TcpState::Closed {
internal_socket.close();
internal_socket
.connect((address, remote.port()), self.get_ephemeral_port())
.map_err(|_| NetworkError::ConnectionFailure)?;
}
}
}
// Avoid using Instant::now() and Advance time manually
self.update(false)?;
{
self.advance_time(1);
}
}
Ok(socket)
}
fn is_connected(&self, socket: &Self::TcpSocket) -> Result<bool, Self::Error> {
let mut sockets = self.sockets.borrow_mut();
let socket: &mut net::socket::TcpSocket = &mut *sockets.get(*socket);
Ok(socket.may_send() && socket.may_recv())
}
fn write(&self, socket: &mut Self::TcpSocket, buffer: &[u8]) -> nb::Result<usize, Self::Error> {
let mut non_queued_bytes = &buffer[..];
while non_queued_bytes.len() != 0 {
let result = {
let mut sockets = self.sockets.borrow_mut();
let socket: &mut net::socket::TcpSocket = &mut *sockets.get(*socket);
let result = socket.send_slice(non_queued_bytes);
result
};
match result {
Ok(num_bytes) => {
// In case the buffer is filled up, push bytes into ethernet driver
if num_bytes != non_queued_bytes.len() {
self.update(true)?;
}
// Process the unwritten bytes again, if any
non_queued_bytes = &non_queued_bytes[num_bytes..]
}
Err(_) => return Err(nb::Error::Other(NetworkError::WriteFailure)),
}
}
Ok(buffer.len())
}
fn read(
&self,
socket: &mut Self::TcpSocket,
buffer: &mut [u8],
) -> nb::Result<usize, Self::Error> {
// Enqueue received bytes into the TCP socket buffer
self.update(true)?;
let mut sockets = self.sockets.borrow_mut();
let socket: &mut net::socket::TcpSocket = &mut *sockets.get(*socket);
let result = socket.recv_slice(buffer);
match result {
Ok(num_bytes) => Ok(num_bytes),
Err(_) => Err(nb::Error::Other(NetworkError::ReadFailure)),
}
}
fn close(&self, socket: Self::TcpSocket) -> Result<(), Self::Error> {
let mut sockets = self.sockets.borrow_mut();
let internal_socket: &mut net::socket::TcpSocket = &mut *sockets.get(socket);
internal_socket.close();
self.unused_handles.borrow_mut().push(socket).unwrap();
Ok(())
}
}

28
src/rx.rs
View File

@ -11,38 +11,38 @@ pub const RSV_LENGTH: usize = 6;
/// Struct for RX Buffer on the hardware
/// TODO: Should be a singleton
pub struct RxBuffer {
start_addr: u16,
wrap_addr: u16,
next_addr: u16,
tail_addr: u16,
tail_addr: u16
}
impl RxBuffer {
pub fn new() -> Self {
RxBuffer {
start_addr: ERXST_DEFAULT,
wrap_addr: ERXST_DEFAULT,
next_addr: ERXST_DEFAULT,
tail_addr: ERXTAIL_DEFAULT,
tail_addr: ERXTAIL_DEFAULT
}
}
pub fn set_start_addr(&mut self, addr: u16) {
self.start_addr = addr;
pub fn set_wrap_addr(&mut self, addr: u16) {
self.wrap_addr = addr;
}
pub fn get_start_addr(&self) -> u16 {
self.start_addr
pub fn get_wrap_addr(& self) -> u16{
self.wrap_addr
}
pub fn set_next_addr(&mut self, addr: u16) {
self.next_addr = addr;
}
pub fn get_next_addr(&self) -> u16 {
pub fn get_next_addr(& self) -> u16{
self.next_addr
}
pub fn set_tail_addr(&mut self, addr: u16) {
self.tail_addr = addr;
}
pub fn get_tail_addr(&self) -> u16 {
pub fn get_tail_addr(& self) -> u16{
self.tail_addr
}
}
@ -52,7 +52,7 @@ impl RxBuffer {
pub struct RxPacket {
rsv: Rsv,
frame: [u8; RAW_FRAME_LENGTH_MAX],
frame_length: usize,
frame_length: usize
}
impl RxPacket {
@ -60,7 +60,7 @@ impl RxPacket {
RxPacket {
rsv: Rsv::new(),
frame: [0; RAW_FRAME_LENGTH_MAX],
frame_length: 0,
frame_length: 0
}
}
@ -106,14 +106,14 @@ impl RxPacket {
struct Rsv {
raw_rsv: [u8; RSV_LENGTH],
// TODO: Add more definitions
frame_length: u16,
frame_length: u16
}
impl Rsv {
fn new() -> Self {
Rsv {
raw_rsv: [0; RSV_LENGTH],
frame_length: 0_u16,
frame_length: 0_u16
}
}

58
src/smoltcp_phy.rs
View File

@ -1,30 +1,32 @@
use crate::{tx, EthPhy, RAW_FRAME_LENGTH_MAX};
use crate::{
EthController, tx, RAW_FRAME_LENGTH_MAX
};
use core::cell;
use smoltcp::{
phy::{Device, DeviceCapabilities, RxToken, TxToken},
time::Instant,
Error,
Error
};
pub struct SmoltcpDevice<E: EthPhy> {
pub eth_phy: cell::RefCell<E>,
pub struct SmoltcpDevice<EC: EthController> {
pub eth_controller: cell::RefCell<EC>,
rx_packet_buf: [u8; RAW_FRAME_LENGTH_MAX],
tx_packet_buf: [u8; RAW_FRAME_LENGTH_MAX],
tx_packet_buf: [u8; RAW_FRAME_LENGTH_MAX]
}
impl<E: EthPhy> SmoltcpDevice<E> {
pub fn new(eth_phy: E) -> Self {
impl<EC: EthController> SmoltcpDevice<EC> {
pub fn new(eth_controller: EC) -> Self {
SmoltcpDevice {
eth_phy: cell::RefCell::new(eth_phy),
eth_controller: cell::RefCell::new(eth_controller),
rx_packet_buf: [0; RAW_FRAME_LENGTH_MAX],
tx_packet_buf: [0; RAW_FRAME_LENGTH_MAX],
tx_packet_buf: [0; RAW_FRAME_LENGTH_MAX]
}
}
}
impl<'a, E: 'a + EthPhy> Device<'a> for SmoltcpDevice<E> {
impl<'a, EC: 'a + EthController> Device<'a> for SmoltcpDevice<EC> {
type RxToken = EthRxToken<'a>;
type TxToken = EthTxToken<'a, E>;
type TxToken = EthTxToken<'a, EC>;
fn capabilities(&self) -> DeviceCapabilities {
let mut caps = DeviceCapabilities::default();
@ -33,33 +35,33 @@ impl<'a, E: 'a + EthPhy> Device<'a> for SmoltcpDevice<E> {
}
fn receive(&'a mut self) -> Option<(Self::RxToken, Self::TxToken)> {
let self_p = (&mut *self) as *mut SmoltcpDevice<E>;
match self.eth_phy.borrow_mut().recv_packet(false) {
let self_p = (&mut *self) as *mut SmoltcpDevice<EC>;
match self.eth_controller.borrow_mut().receive_next(false) {
Ok(rx_packet) => {
// Write received packet to RX packet buffer
rx_packet.write_frame_to(&mut self.rx_packet_buf);
// Construct a RxToken
let rx_token = EthRxToken {
buf: &mut self.rx_packet_buf,
len: rx_packet.get_frame_length(),
len: rx_packet.get_frame_length()
};
// Construct a blank TxToken
let tx_token = EthTxToken {
buf: &mut self.tx_packet_buf,
dev: self_p,
dev: self_p
};
Some((rx_token, tx_token))
}
Err(_) => None,
},
Err(_) => None
}
}
fn transmit(&'a mut self) -> Option<Self::TxToken> {
let self_p = (&mut *self) as *mut SmoltcpDevice<E>;
let self_p = (&mut *self) as *mut SmoltcpDevice<EC>;
// Construct a blank TxToken
let tx_token = EthTxToken {
buf: &mut self.tx_packet_buf,
dev: self_p,
dev: self_p
};
Some(tx_token)
}
@ -67,7 +69,7 @@ impl<'a, E: 'a + EthPhy> Device<'a> for SmoltcpDevice<E> {
pub struct EthRxToken<'a> {
buf: &'a mut [u8],
len: usize,
len: usize
}
impl<'a> RxToken for EthRxToken<'a> {
@ -79,12 +81,12 @@ impl<'a> RxToken for EthRxToken<'a> {
}
}
pub struct EthTxToken<'a, E: EthPhy> {
pub struct EthTxToken<'a, EC: EthController> {
buf: &'a mut [u8],
dev: *mut SmoltcpDevice<E>,
dev: *mut SmoltcpDevice<EC>
}
impl<'a, E: 'a + EthPhy> TxToken for EthTxToken<'a, E> {
impl<'a, EC: 'a + EthController> TxToken for EthTxToken<'a, EC> {
fn consume<R, F>(self, _timestamp: Instant, len: usize, f: F) -> Result<R, Error>
where
F: FnOnce(&mut [u8]) -> Result<R, Error>,
@ -95,10 +97,12 @@ impl<'a, E: 'a + EthPhy> TxToken for EthTxToken<'a, E> {
// Update frame length and write frame bytes
tx_packet.update_frame(&mut self.buf[..len], len);
// Send the packet as raw
let eth_phy = unsafe { &mut (*self.dev).eth_phy };
match eth_phy.borrow_mut().send_packet(&tx_packet) {
Ok(_) => result,
Err(_) => Err(Error::Exhausted),
let eth_controller = unsafe {
&mut (*self.dev).eth_controller
};
match eth_controller.borrow_mut().send_raw_packet(&tx_packet) {
Ok(_) => { result },
Err(_) => Err(Error::Exhausted)
}
}
}

286
src/spi.rs
View File

@ -1,4 +1,7 @@
use embedded_hal::{blocking::spi::Transfer, digital::v2::OutputPin};
use embedded_hal::{
blocking::spi::Transfer,
digital::v2::OutputPin,
};
pub mod interfaces {
use embedded_hal::spi;
@ -12,206 +15,193 @@ pub mod interfaces {
}
pub mod opcodes {
/// 1-byte Instructions
pub const SETETHRST: u8 = 0b1100_1010;
pub const SETPKTDEC: u8 = 0b1100_1100;
pub const SETTXRTS: u8 = 0b1101_0100;
pub const ENABLERX: u8 = 0b1110_1000;
/// 3-byte Instructions
pub const WRXRDPT: u8 = 0b0110_0100; // 8-bit opcode followed by data
pub const RRXRDPT: u8 = 0b0110_0110; // 8-bit opcode followed by data
pub const WGPWRPT: u8 = 0b0110_1100; // 8-bit opcode followed by data
pub const RGPWRPT: u8 = 0b0110_1110; // 8-bit opcode followed by data
/// N-byte Instructions
/// SPI Opcodes
pub const RCRU: u8 = 0b0010_0000;
pub const WCRU: u8 = 0b0010_0010;
pub const RRXDATA: u8 = 0b0010_1100; // 8-bit opcode followed by data
pub const WGPDATA: u8 = 0b0010_1010; // 8-bit opcode followed by data
pub const RERXDATA: u8 = 0b0010_1100; // 8-bit opcode followed by data
pub const WEGPDATA: u8 = 0b0010_1010; // 8-bit opcode followed by data
}
pub mod addrs {
/// SPI Register Mapping
/// Note: PSP interface use different address mapping
// SPI Init Reset Registers
pub const EUDAST: u8 = 0x16; // 16-bit data
pub const ESTAT: u8 = 0x1a; // 16-bit data
pub const ECON2: u8 = 0x6e; // 16-bit data
//
pub const ERXFCON: u8 = 0x34; // 16-bit data
//
pub const MAADR3: u8 = 0x60; // 16-bit data
pub const MAADR2: u8 = 0x62; // 16-bit data
pub const MAADR1: u8 = 0x64; // 16-bit data
// RX Registers
pub const ERXRDPT: u8 = 0x8a; // 16-bit data
pub const ERXST: u8 = 0x04; // 16-bit data
pub const ERXTAIL: u8 = 0x06; // 16-bit data
pub const EIR: u8 = 0x1c; // 16-bit data
pub const ECON1: u8 = 0x1e; // 16-bit data
pub const MAMXFL: u8 = 0x4a; // 16-bit data
// TX Registers
pub const EGPWRPT: u8 = 0x88; // 16-bit data
pub const ETXST: u8 = 0x00; // 16-bit data
pub const ETXSTAT: u8 = 0x12; // 16-bit data
pub const ETXLEN: u8 = 0x02; // 16-bit data
pub const EUDAST: u8 = 0x16; // 16-bit data
pub const ESTAT: u8 = 0x1a; // 16-bit data
pub const ECON2: u8 = 0x6e; // 16-bit data
//
pub const ERXFCON: u8 = 0x34; // 16-bit data
//
pub const MAADR3: u8 = 0x60; // 16-bit data
pub const MAADR2: u8 = 0x62; // 16-bit data
pub const MAADR1: u8 = 0x64; // 16-bit data
// RX Registers
pub const ERXRDPT: u8 = 0x8a; // 16-bit data
pub const ERXST: u8 = 0x04; // 16-bit data
pub const ERXTAIL: u8 = 0x06; // 16-bit data
pub const EIR: u8 = 0x1c; // 16-bit data
pub const ECON1: u8 = 0x1e; // 16-bit data
pub const MAMXFL: u8 = 0x4a; // 16-bit data
// TX Registers
pub const EGPWRPT: u8 = 0x88; // 16-bit data
pub const ETXST: u8 = 0x00; // 16-bit data
pub const ETXSTAT: u8 = 0x12; // 16-bit data
pub const ETXLEN: u8 = 0x02; // 16-bit data
}
/// Struct for SPI I/O interface on ENC424J600
/// Note: stm32f4xx_hal::spi's pins include: SCK, MISO, MOSI
pub struct SpiPort<SPI: Transfer<u8>, NSS: OutputPin> {
pub struct SpiPort<SPI: Transfer<u8>,
NSS: OutputPin,
F: FnMut(u32) -> ()> {
spi: SPI,
nss: NSS,
#[cfg(feature = "cortex-m-cpu")]
cpu_freq_mhz: f32,
delay_ns: F,
}
pub enum Error {
OpcodeError,
TransferError,
pub enum SpiPortError {
TransferError
}
#[allow(unused_must_use)]
impl<SPI: Transfer<u8>, NSS: OutputPin> SpiPort<SPI, NSS> {
impl <SPI: Transfer<u8>,
NSS: OutputPin,
F: FnMut(u32) -> ()> SpiPort<SPI, NSS, F> {
// TODO: return as Result()
pub fn new(spi: SPI, mut nss: NSS) -> Self {
pub fn new(spi: SPI, mut nss: NSS, delay_ns: F) -> Self {
nss.set_high();
SpiPort {
spi,
nss,
#[cfg(feature = "cortex-m-cpu")]
cpu_freq_mhz: 0.,
delay_ns,
}
}
#[cfg(feature = "cortex-m-cpu")]
pub fn cpu_freq_mhz(mut self, freq: u32) -> Self {
self.cpu_freq_mhz = freq as f32;
self
}
pub fn read_reg_8b(&mut self, addr: u8) -> Result<u8, Error> {
pub fn read_reg_8b(&mut self, addr: u8) -> Result<u8, SpiPortError> {
// Using RCRU instruction to read using unbanked (full) address
let mut buf: [u8; 4] = [0; 4];
buf[1] = addr;
self.rw_n(&mut buf, opcodes::RCRU, 2)?;
Ok(buf[2])
let r_data = self.rw_addr_u8(opcodes::RCRU, addr, 0)?;
Ok(r_data)
}
pub fn read_reg_16b(&mut self, lo_addr: u8) -> Result<u16, Error> {
// Unless the register can be written with specific opcode,
// use WCRU instruction to write using unbanked (full) address
let mut buf: [u8; 4] = [0; 4];
let mut data_offset = 0; // number of bytes separating
// actual data from opcode
match lo_addr {
addrs::ERXRDPT | addrs::EGPWRPT => {}
_ => {
buf[1] = lo_addr;
data_offset = 1;
}
}
self.rw_n(
&mut buf,
match lo_addr {
addrs::ERXRDPT => opcodes::RRXRDPT,
addrs::EGPWRPT => opcodes::RGPWRPT,
_ => opcodes::RCRU,
},
2 + data_offset, // extra 8-bit lo_addr before data
)?;
Ok(buf[data_offset + 1] as u16 | (buf[data_offset + 2] as u16) << 8)
pub fn read_reg_16b(&mut self, lo_addr: u8) -> Result<u16, SpiPortError> {
let r_data_lo = self.read_reg_8b(lo_addr)?;
let r_data_hi = self.read_reg_8b(lo_addr + 1)?;
// Combine top and bottom 8-bit to return 16-bit
Ok(((r_data_hi as u16) << 8) | r_data_lo as u16)
}
// Currently requires manual slicing (buf[1..]) for the data read back
pub fn read_rxdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize) -> Result<(), Error> {
self.rw_n(buf, opcodes::RRXDATA, data_length)
pub fn read_rxdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize)
-> Result<(), SpiPortError> {
let r_valid = self.r_n(buf, opcodes::RERXDATA, data_length)?;
Ok(r_valid)
}
// Currently requires actual data to be stored in buf[1..] instead of buf[0..]
// Currenly requires actual data to be stored in buf[1..] instead of buf[0..]
// TODO: Maybe better naming?
pub fn write_txdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize) -> Result<(), Error> {
self.rw_n(buf, opcodes::WGPDATA, data_length)
pub fn write_txdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize)
-> Result<(), SpiPortError> {
let w_valid = self.w_n(buf, opcodes::WEGPDATA, data_length)?;
Ok(w_valid)
}
pub fn write_reg_8b(&mut self, addr: u8, data: u8) -> Result<(), Error> {
pub fn write_reg_8b(&mut self, addr: u8, data: u8) -> Result<(), SpiPortError> {
// TODO: addr should be separated from w_data
// Using WCRU instruction to write using unbanked (full) address
let mut buf: [u8; 3] = [0; 3];
buf[1] = addr;
buf[2] = data;
self.rw_n(&mut buf, opcodes::WCRU, 2)
self.rw_addr_u8(opcodes::WCRU, addr, data)?;
Ok(())
}
pub fn write_reg_16b(&mut self, lo_addr: u8, data: u16) -> Result<(), Error> {
// Unless the register can be written with specific opcode,
// use WCRU instruction to write using unbanked (full) address
let mut buf: [u8; 4] = [0; 4];
let mut data_offset = 0; // number of bytes separating
// actual data from opcode
match lo_addr {
addrs::ERXRDPT | addrs::EGPWRPT => {}
_ => {
buf[1] = lo_addr;
data_offset = 1;
}
}
buf[1 + data_offset] = data as u8;
buf[2 + data_offset] = (data >> 8) as u8;
self.rw_n(
&mut buf,
match lo_addr {
addrs::ERXRDPT => opcodes::WRXRDPT,
addrs::EGPWRPT => opcodes::WGPWRPT,
_ => opcodes::WCRU,
},
2 + data_offset, // extra 8-bit lo_addr before data
)
pub fn write_reg_16b(&mut self, lo_addr: u8, data: u16) -> Result<(), SpiPortError> {
self.write_reg_8b(lo_addr, (data & 0xff) as u8)?;
self.write_reg_8b(lo_addr + 1, ((data & 0xff00) >> 8) as u8)?;
Ok(())
}
pub fn send_opcode(&mut self, opcode: u8) -> Result<(), Error> {
match opcode {
opcodes::SETETHRST | opcodes::SETPKTDEC | opcodes::SETTXRTS | opcodes::ENABLERX => {
let mut buf: [u8; 1] = [0];
self.rw_n(&mut buf, opcode, 0)
}
_ => Err(Error::OpcodeError),
}
pub fn delay_us(&mut self, duration: u32) {
(self.delay_ns)(duration * 1000)
}
// TODO: Actual data should start from buf[0], not buf[1]
// Completes an SPI transfer for reading data to the given buffer,
// or writing data from the buffer.
// It sends an 8-bit instruction, followed by either
// receiving or sending n*8-bit data.
// The slice of buffer provided must begin with the 8-bit instruction.
// If n = 0, the transfer will only involve sending the instruction.
fn rw_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize) -> Result<(), Error> {
assert!(buf.len() > data_length);
// TODO: Generalise transfer functions
// TODO: (Make data read/write as reference to array)
// Currently requires 1-byte addr, read/write data is only 1-byte
fn rw_addr_u8(&mut self, opcode: u8, addr: u8, data: u8)
-> Result<u8, SpiPortError> {
// Enable chip select
self.nss.set_low();
// Start writing to SLAVE
// TODO: don't just use 3 bytes
let mut buf: [u8; 3] = [0; 3];
buf[0] = opcode;
buf[1] = addr;
buf[2] = data;
match self.spi.transfer(&mut buf) {
Ok(_) => {
// Disable chip select
(self.delay_ns)(60);
self.nss.set_high();
(self.delay_ns)(30);
Ok(buf[2])
},
// TODO: Maybe too naive?
Err(_) => {
// Disable chip select
(self.delay_ns)(60);
self.nss.set_high();
(self.delay_ns)(30);
Err(SpiPortError::TransferError)
}
}
}
// TODO: Generalise transfer functions
// Currently does NOT accept addr, read data is N-byte long
// Returns a reference to the data returned
// Note: buf must be at least (data_length + 1)-byte long
// TODO: Check and raise error for array size < (data_length + 1)
fn r_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize)
-> Result<(), SpiPortError> {
// Enable chip select
self.nss.set_low();
// >=50ns min. CS_n setup time
#[cfg(feature = "cortex-m-cpu")]
cortex_m::asm::delay((0.05 * (self.cpu_freq_mhz + 1.)) as u32);
// Start writing to SLAVE
buf[0] = opcode;
let result = self.spi.transfer(&mut buf[..data_length + 1]);
match opcode {
opcodes::RCRU | opcodes::WCRU | opcodes::RRXDATA | opcodes::WGPDATA => {
match self.spi.transfer(&mut buf[..data_length+1]) {
Ok(_) => {
// Disable chip select
// >=50ns min. CS_n hold time
#[cfg(feature = "cortex-m-cpu")]
cortex_m::asm::delay((0.05 * (self.cpu_freq_mhz + 1.)) as u32);
self.nss.set_high();
// >=20ns min. CS_n disable time
#[cfg(feature = "cortex-m-cpu")]
cortex_m::asm::delay((0.02 * (self.cpu_freq_mhz + 1.)) as u32);
}
_ => {}
}
match result {
Ok(_) => Ok(()),
Ok(())
},
// TODO: Maybe too naive?
Err(_) => Err(Error::TransferError),
Err(_) => {
// Disable chip select
self.nss.set_high();
Err(SpiPortError::TransferError)
}
}
}
// Note: buf[0] is currently reserved for opcode to overwrite
// TODO: Actual data should start from buf[0], not buf[1]
fn w_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize)
-> Result<(), SpiPortError> {
// Enable chip select
self.nss.set_low();
// Start writing to SLAVE
buf[0] = opcode;
// TODO: Maybe need to copy data to buf later on
match self.spi.transfer(&mut buf[..data_length+1]) {
Ok(_) => {
// Disable chip select
self.nss.set_high();
Ok(())
},
// TODO: Maybe too naive?
Err(_) => {
// Disable chip select
self.nss.set_high();
Err(SpiPortError::TransferError)
}
}
}
}

30
src/tx.rs
View File

@ -1,41 +1,45 @@
use crate::RAW_FRAME_LENGTH_MAX;
/// SRAM Addresses
pub const GPBUFST_DEFAULT: u16 = 0x0000; // Start of General-Purpose SRAM Buffer
pub const GPBUFEN_DEFAULT: u16 = 0x5340; // End of General-Purpose SRAM Buffer == ERXST default
/// Struct for TX Buffer on the hardware
/// TODO: Should be a singleton
pub struct TxBuffer {
start_addr: u16,
wrap_addr: u16,
// The following two fields are controlled by firmware
next_addr: u16,
tail_addr: u16,
tail_addr: u16
}
impl TxBuffer {
pub fn new() -> Self {
TxBuffer {
start_addr: 0x0000,
next_addr: 0x0001,
tail_addr: 0x0000,
wrap_addr: GPBUFST_DEFAULT,
next_addr: GPBUFST_DEFAULT + 1,
tail_addr: GPBUFST_DEFAULT
}
}
pub fn set_start_addr(&mut self, addr: u16) {
self.start_addr = addr;
pub fn set_wrap_addr(&mut self, addr: u16) {
self.wrap_addr = addr;
}
pub fn get_start_addr(&self) -> u16 {
self.start_addr
pub fn get_wrap_addr(& self) -> u16{
self.wrap_addr
}
pub fn set_next_addr(&mut self, addr: u16) {
self.next_addr = addr;
}
pub fn get_next_addr(&self) -> u16 {
pub fn get_next_addr(& self) -> u16{
self.next_addr
}
pub fn set_tail_addr(&mut self, addr: u16) {
self.tail_addr = addr;
}
pub fn get_tail_addr(&self) -> u16 {
pub fn get_tail_addr(& self) -> u16{
self.tail_addr
}
}
@ -44,14 +48,14 @@ impl TxBuffer {
/// TODO: Generalise MAC addresses
pub struct TxPacket {
frame: [u8; RAW_FRAME_LENGTH_MAX],
frame_length: usize,
frame_length: usize
}
impl TxPacket {
pub fn new() -> Self {
TxPacket {
frame: [0; RAW_FRAME_LENGTH_MAX],
frame_length: 0,
frame_length: 0
}
}