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3 Commits
Author | SHA1 | Date |
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occheung | 736d63dcad | |
occheung | d7ba11611b | |
occheung | 61182a8ef0 |
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@ -16,7 +16,7 @@ pub mod tx;
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pub mod smoltcp_phy;
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pub mod smoltcp_phy;
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/// Max raw frame array size
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/// Max raw frame array size
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pub const RAW_FRAME_LENGTH_MAX: usize = 0x1000;
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pub const RAW_FRAME_LENGTH_MAX: usize = 1518;
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pub trait EthController {
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pub trait EthController {
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fn init_dev(&mut self, delay: &mut impl DelayUs<u16>) -> Result<(), EthControllerError>;
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fn init_dev(&mut self, delay: &mut impl DelayUs<u16>) -> Result<(), EthControllerError>;
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@ -29,6 +29,7 @@ pub trait EthController {
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}
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}
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/// TODO: Improve these error types
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/// TODO: Improve these error types
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#[derive(Debug)]
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pub enum EthControllerError {
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pub enum EthControllerError {
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SpiPortError,
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SpiPortError,
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GeneralError,
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GeneralError,
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@ -131,13 +131,17 @@ impl <SPI: Transfer<u8>,
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match self.spi.transfer(&mut buf) {
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match self.spi.transfer(&mut buf) {
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Ok(_) => {
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Ok(_) => {
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// Disable chip select
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// Disable chip select
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cortex_m::asm::delay(10_u32);
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self.nss.set_high();
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self.nss.set_high();
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cortex_m::asm::delay(4_u32);
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Ok(buf[2])
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Ok(buf[2])
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},
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},
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// TODO: Maybe too naive?
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// TODO: Maybe too naive?
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Err(_) => {
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Err(_) => {
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// Disable chip select
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// Disable chip select
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cortex_m::asm::delay(10_u32);
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self.nss.set_high();
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self.nss.set_high();
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cortex_m::asm::delay(4_u32);
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Err(SpiPortError::TransferError)
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Err(SpiPortError::TransferError)
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}
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}
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}
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}
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