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fix-spi-cl
Author | SHA1 | Date |
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Harry Ho | 2da2a91572 |
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@ -117,7 +117,7 @@ const APP: () = {
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.cfgr
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.cfgr
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.sysclk(168.mhz())
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.sysclk(168.mhz())
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.hclk(168.mhz())
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.hclk(168.mhz())
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.pclk1(42.mhz())
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.pclk2(42.mhz()) // used by SPI1
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.require_pll48clk()
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.require_pll48clk()
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.freeze();
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.freeze();
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let mut delay = Delay::new(c.core.SYST, clocks);
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let mut delay = Delay::new(c.core.SYST, clocks);
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@ -149,7 +149,7 @@ const APP: () = {
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let spi_eth_port = Spi::spi1(
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let spi_eth_port = Spi::spi1(
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spi1, (spi1_sck, spi1_miso, spi1_mosi),
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spi1, (spi1_sck, spi1_miso, spi1_mosi),
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enc424j600::spi::interfaces::SPI_MODE,
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enc424j600::spi::interfaces::SPI_MODE,
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Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ),
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10_500_000.hz(), // PCLK2 @ 42MHz, set SPI1 baud rate as f_PCLK2 divided by 4
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clocks);
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clocks);
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SpiEth::new(spi_eth_port, spi1_nss)
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SpiEth::new(spi_eth_port, spi1_nss)
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@ -49,9 +49,7 @@ const APP: () = {
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.cfgr
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.cfgr
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.sysclk(168.mhz())
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.sysclk(168.mhz())
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.hclk(168.mhz())
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.hclk(168.mhz())
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//.pclk1(32.mhz())
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.pclk2(42.mhz()) // used by SPI1
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.pclk1(42.mhz())
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//.pclk2(64.mhz())
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.require_pll48clk()
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.require_pll48clk()
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.freeze();
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.freeze();
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let mut delay = Delay::new(c.core.SYST, clocks);
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let mut delay = Delay::new(c.core.SYST, clocks);
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@ -80,7 +78,7 @@ const APP: () = {
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let spi_eth_port = Spi::spi1(
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let spi_eth_port = Spi::spi1(
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spi1, (spi1_sck, spi1_miso, spi1_mosi),
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spi1, (spi1_sck, spi1_miso, spi1_mosi),
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enc424j600::spi::interfaces::SPI_MODE,
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enc424j600::spi::interfaces::SPI_MODE,
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Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ),
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10_500_000.hz(), // PCLK2 @ 42MHz, set SPI1 baud rate as f_PCLK2 divided by 4
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clocks);
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clocks);
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SpiEth::new(spi_eth_port, spi1_nss)
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SpiEth::new(spi_eth_port, spi1_nss)
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