Add packet RX
This commit is contained in:
parent
4e4267e55a
commit
9b48a585cf
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@ -13,10 +13,10 @@ volatile-register = "0.2"
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aligned = "0.3"
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aligned = "0.3"
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stm32f4xx-hal = { version = "0.8" , optional = true }
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stm32f4xx-hal = { version = "0.8" , optional = true }
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smoltcp = { version = "0.6.0", default-features = false, features = ["proto-ipv4", "proto-ipv6", "socket-icmp", "socket-udp", "socket-tcp", "log", "verbose", "ethernet"], optional = true }
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smoltcp = { version = "0.6.0", default-features = false, features = ["proto-ipv4", "proto-ipv6", "socket-icmp", "socket-udp", "socket-tcp", "log", "verbose", "ethernet"], optional = true }
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log = { version = "0.4", optional = true }
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log = { version = "0.4" }
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[features]
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[features]
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smoltcp-phy = ["smoltcp", "log"]
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smoltcp-phy = ["smoltcp"]
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stm32f407 = ["stm32f4xx-hal/stm32f407"]
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stm32f407 = ["stm32f4xx-hal/stm32f407"]
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default = []
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default = []
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151
src/lib.rs
151
src/lib.rs
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@ -1,4 +1,155 @@
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#![no_std]
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#![no_std]
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use core::fmt;
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/// STM32F4xx-HAL specific implementations
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/// STM32F4xx-HAL specific implementations
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pub mod spi;
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pub mod spi;
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use stm32f4xx_hal::{
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hal::{
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blocking::spi::Transfer,
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digital::v2::OutputPin,
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}
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};
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pub mod rx;
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#[cfg(feature="smoltcp")]
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pub mod smoltcp_phy;
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pub trait EthController {
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fn init_dev(&mut self) -> Result<(), EthControllerError>;
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fn init_rxbuf(&mut self) -> Result<(), EthControllerError>;
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fn receive_next(&mut self) -> Result<rx::RxPacket, EthControllerError>;
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fn set_promiscuous(&mut self) -> Result<(), EthControllerError>;
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fn read_from_mac(&mut self, mac: &mut [u8]) -> Result<(), EthControllerError>;
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}
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/// TODO: Improve these error types
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pub enum EthControllerError {
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SpiPortError,
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GeneralError
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}
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impl From<spi::SpiPortError> for EthControllerError {
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fn from(e: spi::SpiPortError) -> EthControllerError {
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EthControllerError::SpiPortError
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}
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}
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/// Ethernet controller using SPI interface
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pub struct SpiEth<SPI: Transfer<u8>,
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NSS: OutputPin> {
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spi_port: spi::SpiPort<SPI, NSS>,
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rx_buf: rx::RxBuffer
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}
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impl <SPI: Transfer<u8>,
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NSS: OutputPin> SpiEth<SPI, NSS> {
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pub fn new(spi: SPI, mut nss: NSS) -> Self {
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SpiEth {
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spi_port: spi::SpiPort::new(spi, nss),
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rx_buf: rx::RxBuffer::new(),
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// TODO: tx_buf
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}
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}
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}
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impl <SPI: Transfer<u8>,
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NSS: OutputPin> EthController for SpiEth<SPI, NSS> {
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fn init_dev(&mut self) -> Result<(), EthControllerError> {
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// Write 0x1234 to EUDAST
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self.spi_port.write_reg_16b(spi::EUDAST, 0x1234)?;
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// Verify that EUDAST is 0x1234
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let mut eudast = self.spi_port.read_reg_16b(spi::EUDAST)?;
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if eudast != 0x1234 {
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return Err(EthControllerError::GeneralError)
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}
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// Poll CLKRDY (ESTAT<12>) to check if it is set
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loop {
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let estat = self.spi_port.read_reg_16b(spi::ESTAT)?;
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if estat & 0x1000 == 0x1000 { break }
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}
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// Set ETHRST (ECON2<4>) to 1
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let econ2 = self.spi_port.read_reg_8b(spi::ECON2)?;
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self.spi_port.write_reg_8b(spi::ECON2, 0x10 | (econ2 & 0b11101111))?;
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// Verify that EUDAST is 0x0000
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eudast = self.spi_port.read_reg_16b(spi::EUDAST)?;
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if eudast != 0x0000 {
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return Err(EthControllerError::GeneralError)
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}
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Ok(())
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}
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fn init_rxbuf(&mut self) -> Result<(), EthControllerError> {
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// Set ERXST pointer
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self.spi_port.write_reg_16b(spi::ERXST, self.rx_buf.get_wrap_addr());
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// Set ERXTAIL pointer
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self.spi_port.write_reg_16b(spi::ERXTAIL, self.rx_buf.get_tail_addr());
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// Set MAMXFL to maximum number of bytes in each accepted packet
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self.spi_port.write_reg_16b(spi::MAMXFL, rx::RAW_FRAME_LENGTH_MAX as u16);
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// Enable RXEN (ECON1<0>)
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let econ1 = self.spi_port.read_reg_16b(spi::ECON1)?;
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self.spi_port.write_reg_16b(spi::ECON1, 0x1 | (econ1 & 0xfffe));
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Ok(())
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}
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/// Receive the next packet
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fn receive_next(&mut self) -> Result<rx::RxPacket, EthControllerError> {
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// Poll PKTIF (EIR<4>) to check if it is set
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loop {
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let eir = self.spi_port.read_reg_16b(spi::EIR)?;
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if eir & 0x40 == 0x40 { break }
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}
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// Set ERXRDPT pointer to next_addr
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self.spi_port.write_reg_16b(spi::ERXRDPT, self.rx_buf.get_next_addr())?;
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// Read 2 bytes to update next_addr
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let mut next_addr_buf = [0; 3];
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self.spi_port.read_rxdat(&mut next_addr_buf, 2)?;
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self.rx_buf.set_next_addr((next_addr_buf[1] as u16) | ((next_addr_buf[2] as u16) << 8));
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// Read 6 bytes to update rsv
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let mut rsv_buf = [0; 7];
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self.spi_port.read_rxdat(&mut rsv_buf, 6)?;
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// Construct an RxPacket
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// TODO: can we directly assign to fields instead of using functions?
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let mut rx_packet = rx::RxPacket::new();
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// Get and update frame length
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rx_packet.write_to_rsv(&rsv_buf[1..]);
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rx_packet.update_frame_length();
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// Read frame bytes
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let mut frame_buf = [0; rx::RAW_FRAME_LENGTH_MAX];
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self.spi_port.read_rxdat(&mut frame_buf, rx_packet.get_frame_length() as u32)?;
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rx_packet.write_to_frame(&frame_buf[1..]);
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// Set ERXTAIL pointer to (next_addr - 2)
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if self.rx_buf.get_next_addr() > rx::ERXST_DEFAULT {
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self.spi_port.write_reg_16b(spi::ERXTAIL, self.rx_buf.get_next_addr() - 2)?;
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} else {
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self.spi_port.write_reg_16b(spi::ERXTAIL, rx::RX_MAX_ADDRESS - 1)?;
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}
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// Set PKTDEC to decrement PKTCNT
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let econ1_hi = self.spi_port.read_reg_8b(spi::ECON1 + 1)?;
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self.spi_port.write_reg_8b(spi::ECON1 + 1, 0x01 | (econ1_hi & 0xfe))?;
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// Return the RxPacket
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Ok(rx_packet)
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}
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/// Set controller to Promiscuous Mode
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fn set_promiscuous(&mut self) -> Result<(), EthControllerError> {
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// From ENC424J600 Data Sheet Section 10.12:
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// "To accept all incoming frames regardless of content (Promiscuous mode),
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// set the CRCEN, RUNTEN, UCEN, NOTMEEN and MCEN bits."
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let mut erxfcon_lo = self.spi_port.read_reg_8b(spi::ERXFCON)?;
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self.spi_port.write_reg_8b(spi::ERXFCON, 0b0101_1110 | (erxfcon_lo & 0b1010_0001));
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Ok(())
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}
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/// Read MAC to [u8; 6]
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fn read_from_mac(&mut self, mac: &mut [u8]) -> Result<(), EthControllerError> {
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mac[0] = self.spi_port.read_reg_8b(spi::MAADR1)?;
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mac[1] = self.spi_port.read_reg_8b(spi::MAADR1 + 1)?;
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mac[2] = self.spi_port.read_reg_8b(spi::MAADR2)?;
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mac[3] = self.spi_port.read_reg_8b(spi::MAADR2 + 1)?;
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mac[4] = self.spi_port.read_reg_8b(spi::MAADR3)?;
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mac[5] = self.spi_port.read_reg_8b(spi::MAADR3 + 1)?;
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Ok(())
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}
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}
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@ -0,0 +1,125 @@
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/// SRAM Addresses
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pub const ERXST_DEFAULT: u16 = 0x5340;
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pub const ERXTAIL_DEFAULT: u16 = 0x5ffe;
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pub const RX_MAX_ADDRESS: u16 = 0x5fff;
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/// Max raw frame array size
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pub const RAW_FRAME_LENGTH_MAX: usize = 0x1000;
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/// Receive Status Vector Length
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pub const RSV_LENGTH: usize = 6;
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/// Struct for RX Buffer
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/// TODO: Should be a singleton
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pub struct RxBuffer {
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wrap_addr: u16,
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next_addr: u16,
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tail_addr: u16
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}
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impl RxBuffer {
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pub fn new() -> Self {
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RxBuffer {
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wrap_addr: ERXST_DEFAULT,
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next_addr: ERXST_DEFAULT,
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tail_addr: ERXTAIL_DEFAULT
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}
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}
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pub fn set_wrap_addr(&mut self, addr: u16) {
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self.wrap_addr = addr;
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}
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pub fn get_wrap_addr(& self) -> u16{
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self.wrap_addr
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}
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pub fn set_next_addr(&mut self, addr: u16) {
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self.next_addr = addr;
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}
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pub fn get_next_addr(& self) -> u16{
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self.next_addr
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}
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pub fn set_tail_addr(&mut self, addr: u16) {
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self.tail_addr = addr;
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}
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pub fn get_tail_addr(& self) -> u16{
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self.tail_addr
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}
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}
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/// Struct for RX Packet
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/// TODO: Generalise MAC addresses
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pub struct RxPacket {
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rsv: Rsv,
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frame: [u8; RAW_FRAME_LENGTH_MAX],
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frame_length: usize
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}
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impl RxPacket {
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pub fn new() -> Self {
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RxPacket {
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rsv: Rsv::new(),
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frame: [0; RAW_FRAME_LENGTH_MAX],
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frame_length: 0
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}
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}
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pub fn write_to_rsv(&mut self, raw_rsv: &[u8]) {
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self.rsv.write_to_rsv(raw_rsv);
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}
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pub fn read_raw_rsv(&self) -> &[u8] {
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self.rsv.read_raw_rsv()
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}
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pub fn update_frame_length(&mut self) {
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self.rsv.set_frame_length();
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self.frame_length = self.rsv.get_frame_length() as usize;
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}
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pub fn get_frame_length(&self) -> usize {
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self.frame_length
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}
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pub fn write_to_frame(&mut self, raw_frame: &[u8]) {
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for i in 0..self.frame_length {
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self.frame[i] = raw_frame[i];
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}
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}
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pub fn get_frame_byte(&self, i: usize) -> u8 {
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self.frame[i]
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}
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}
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/// Struct for Receive Status Vector
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/// See: Table 9-1, ENC424J600 Data Sheet
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struct Rsv {
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raw_rsv: [u8; RSV_LENGTH],
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// TODO: Add more definitions
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frame_length: u16
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}
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impl Rsv {
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fn new() -> Self {
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Rsv {
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raw_rsv: [0; RSV_LENGTH],
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frame_length: 0_u16
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}
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}
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fn write_to_rsv(&mut self, raw_rsv: &[u8]) {
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for i in 0..RSV_LENGTH {
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self.raw_rsv[i] = raw_rsv[i];
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}
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}
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fn read_raw_rsv(&self) -> &[u8] {
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&self.raw_rsv
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}
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fn set_frame_length(&mut self) {
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self.frame_length = (self.raw_rsv[0] as u16) | ((self.raw_rsv[1] as u16) << 8);
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}
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fn get_frame_length(&self) -> u16 {
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self.frame_length
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}
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}
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115
src/spi.rs
115
src/spi.rs
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@ -7,6 +7,10 @@ use stm32f4xx_hal::{
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time::MegaHertz,
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time::MegaHertz,
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spi,
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spi,
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};
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};
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///
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/// FIXME: Move the following to somewhere else
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///
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use crate::rx;
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/// Must use SPI mode cpol=0, cpha=0
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/// Must use SPI mode cpol=0, cpha=0
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pub const SPI_MODE: spi::Mode = spi::Mode {
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pub const SPI_MODE: spi::Mode = spi::Mode {
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@ -17,8 +21,29 @@ pub const SPI_MODE: spi::Mode = spi::Mode {
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pub const SPI_CLOCK: MegaHertz = MegaHertz(14);
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pub const SPI_CLOCK: MegaHertz = MegaHertz(14);
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/// SPI Opcodes
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/// SPI Opcodes
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const RCRU: u8 = 0b00100000;
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const RCRU: u8 = 0b0010_0000;
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const WCRU: u8 = 0b00100010;
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const WCRU: u8 = 0b0010_0010;
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const ERXDATA: u8 = 0b0010_1100; // Treated as 8-bit opcode followed by data
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/// SPI Register Mapping
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/// Note: PSP interface use different address mapping
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// SPI Init Reset Registers
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pub const EUDAST: u8 = 0x16; // 16-bit data
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pub const ESTAT: u8 = 0x1a; // 16-bit data
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pub const ECON2: u8 = 0x6e; // 16-bit data
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//
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pub const ERXFCON: u8 = 0x34; // 16-bit data
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//
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pub const MAADR3: u8 = 0x60; // 16-bit data
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pub const MAADR2: u8 = 0x62; // 16-bit data
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pub const MAADR1: u8 = 0x64; // 16-bit data
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// RX Registers
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pub const ERXRDPT: u8 = 0x8a; // 16-bit data
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pub const ERXST: u8 = 0x04; // 16-bit data
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pub const ERXTAIL: u8 = 0x06; // 16-bit data
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pub const EIR: u8 = 0x1c; // 16-bit data
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pub const ECON1: u8 = 0x1e; // 16-bit data
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pub const MAMXFL: u8 = 0x4a; // 16-bit data
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/// Struct for SPI I/O interface on ENC424J600
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/// Struct for SPI I/O interface on ENC424J600
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/// Note: stm32f4xx_hal::spi's pins include: SCK, MISO, MOSI
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/// Note: stm32f4xx_hal::spi's pins include: SCK, MISO, MOSI
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@ -28,9 +53,12 @@ pub struct SpiPort<SPI: Transfer<u8>,
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nss: NSS,
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nss: NSS,
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}
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}
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impl <SPI: Transfer<u8, Error = E>,
|
pub enum SpiPortError {
|
||||||
NSS: OutputPin,
|
TransferError
|
||||||
E: fmt::Debug> SpiPort<SPI, NSS> {
|
}
|
||||||
|
|
||||||
|
impl <SPI: Transfer<u8>,
|
||||||
|
NSS: OutputPin> SpiPort<SPI, NSS> {
|
||||||
// TODO: return as Result()
|
// TODO: return as Result()
|
||||||
pub fn new(spi: SPI, mut nss: NSS) -> Self {
|
pub fn new(spi: SPI, mut nss: NSS) -> Self {
|
||||||
nss.set_high();
|
nss.set_high();
|
||||||
|
@ -41,29 +69,44 @@ impl <SPI: Transfer<u8, Error = E>,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn read_reg_8b(&mut self, addr: u8) -> Result<u8, SPI::Error> {
|
pub fn read_reg_8b(&mut self, addr: u8) -> Result<u8, SpiPortError> {
|
||||||
// Using RCRU instruction to read using unbanked (full) address
|
// Using RCRU instruction to read using unbanked (full) address
|
||||||
let mut r_data = self.transfer(RCRU, addr, 0)?;
|
let mut r_data = self.rw_addr_u8(RCRU, addr, 0)?;
|
||||||
Ok(r_data)
|
Ok(r_data)
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn read_reg_16b(&mut self, lo_addr: u8) -> Result<u16, SPI::Error> {
|
pub fn read_reg_16b(&mut self, lo_addr: u8) -> Result<u16, SpiPortError> {
|
||||||
let mut r_data_lo = self.read_reg_8b(lo_addr)?;
|
let mut r_data_lo = self.read_reg_8b(lo_addr)?;
|
||||||
let mut r_data_hi = self.read_reg_8b(lo_addr + 1)?;
|
let mut r_data_hi = self.read_reg_8b(lo_addr + 1)?;
|
||||||
// Combine top and bottom 8-bit to return 16-bit
|
// Combine top and bottom 8-bit to return 16-bit
|
||||||
Ok(((r_data_hi as u16) << 8) | r_data_lo as u16)
|
Ok(((r_data_hi as u16) << 8) | r_data_lo as u16)
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn write_reg_8b(&mut self, addr: u8, data: u8) -> Result<u8, SPI::Error> {
|
// Currently requires manual slicing (buf[1:]) for the data read back
|
||||||
// TODO: addr should be separated from w_data
|
pub fn read_rxdat<'a>(&mut self, buf: &'a mut [u8], data_length: u32)
|
||||||
// Using WCRU instruction to write using unbanked (full) address
|
-> Result<u8, SpiPortError> {
|
||||||
self.transfer(WCRU, addr, data)?;
|
let r_valid = self.r_n(buf, ERXDATA, data_length)?;
|
||||||
Ok(0x01) // TODO: should not be just 0x01
|
Ok(r_valid)
|
||||||
}
|
}
|
||||||
|
|
||||||
fn transfer(&mut self, opcode: u8, addr: u8, data: u8)
|
pub fn write_reg_8b(&mut self, addr: u8, data: u8) -> Result<(), SpiPortError> {
|
||||||
-> Result<u8, SPI::Error> {
|
// TODO: addr should be separated from w_data
|
||||||
// TODO: Currently assumes read/write data is only 1-byte
|
// Using WCRU instruction to write using unbanked (full) address
|
||||||
|
self.rw_addr_u8(WCRU, addr, data)?;
|
||||||
|
Ok(())
|
||||||
|
}
|
||||||
|
|
||||||
|
pub fn write_reg_16b(&mut self, lo_addr: u8, data: u16) -> Result<(), SpiPortError> {
|
||||||
|
self.write_reg_8b(lo_addr, (data & 0xff) as u8)?;
|
||||||
|
self.write_reg_8b(lo_addr + 1, ((data & 0xff00) >> 8) as u8)?;
|
||||||
|
Ok(())
|
||||||
|
}
|
||||||
|
|
||||||
|
// TODO: Generalise transfer functions
|
||||||
|
// TODO: (Make data read/write as reference to array)
|
||||||
|
// Currently requires 1-byte addr, read/write data is only 1-byte
|
||||||
|
fn rw_addr_u8(&mut self, opcode: u8, addr: u8, data: u8)
|
||||||
|
-> Result<u8, SpiPortError> {
|
||||||
// Enable chip select
|
// Enable chip select
|
||||||
self.nss.set_low();
|
self.nss.set_low();
|
||||||
// Start writing to SLAVE
|
// Start writing to SLAVE
|
||||||
|
@ -72,13 +115,45 @@ impl <SPI: Transfer<u8, Error = E>,
|
||||||
buf[0] = opcode;
|
buf[0] = opcode;
|
||||||
buf[1] = addr;
|
buf[1] = addr;
|
||||||
buf[2] = data;
|
buf[2] = data;
|
||||||
let result = self.spi.transfer(&mut buf);
|
match self.spi.transfer(&mut buf) {
|
||||||
|
Ok(_) => {
|
||||||
// Disable chip select
|
// Disable chip select
|
||||||
self.nss.set_high();
|
self.nss.set_high();
|
||||||
|
Ok(buf[2])
|
||||||
|
},
|
||||||
|
// TODO: Maybe too naive?
|
||||||
|
Err(e) => {
|
||||||
|
// Disable chip select
|
||||||
|
self.nss.set_high();
|
||||||
|
Err(SpiPortError::TransferError)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
match result {
|
// TODO: Generalise transfer functions
|
||||||
Ok(_) => Ok(buf[2]),
|
// Currently does NOT accept addr, read data is N-byte long
|
||||||
Err(e) => Err(e),
|
// Returns a reference to the data returned
|
||||||
|
// Note: buf must be at least (data_length + 1)-byte long
|
||||||
|
// TODO: Check and raise error for array size < (data_length + 1)
|
||||||
|
fn r_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: u32)
|
||||||
|
-> Result<u8, SpiPortError> {
|
||||||
|
// Enable chip select
|
||||||
|
self.nss.set_low();
|
||||||
|
// Start writing to SLAVE
|
||||||
|
buf[0] = opcode;
|
||||||
|
match self.spi.transfer(buf) {
|
||||||
|
// TODO: Now returns a boolean, maybe use Option<u8> later on?
|
||||||
|
Ok(_) => {
|
||||||
|
// Disable chip select
|
||||||
|
self.nss.set_high();
|
||||||
|
Ok(1)
|
||||||
|
},
|
||||||
|
// TODO: Maybe too naive?
|
||||||
|
Err(e) => {
|
||||||
|
// Disable chip select
|
||||||
|
self.nss.set_high();
|
||||||
|
Err(SpiPortError::TransferError)
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
Loading…
Reference in New Issue