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Reorganise spi consts

This commit is contained in:
Harry Ho 2020-08-17 15:51:25 +08:00
parent 755a77050e
commit 5b99525cd0
4 changed files with 89 additions and 81 deletions
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7
examples/tcp_stm32f407.rs
View File

@ -128,7 +128,8 @@ fn main() -> ! {
// Create SPI1 for HAL
let spi_eth_port = Spi::spi1(
spi1, (spi1_sck, spi1_miso, spi1_mosi),
enc424j600::spi::SPI_MODE, enc424j600::spi::SPI_CLOCK.into(),
enc424j600::spi::interfaces::SPI_MODE,
enc424j600::spi::interfaces::SPI_CLOCK.into(),
clocks);
let mut spi_eth = enc424j600::SpiEth::new(spi_eth_port, spi1_nss);
// Init
@ -215,7 +216,7 @@ fn main() -> ! {
let mut socket = socket_set.get::<TcpSocket>(echo_handle);
if !socket.is_open() {
iprintln!(stim0,
"[{}] Listening to port 1234 for echoing, auto-closing in 10s", instant);
"[{}] Listening to port 1234 for echoing, time-out in 10s", instant);
socket.listen(1234).unwrap();
socket.set_timeout(Some(Duration::from_millis(10000)));
}
@ -232,7 +233,7 @@ fn main() -> ! {
if !socket.is_open() {
iprintln!(stim0,
"[{}] Listening to port 4321 for greeting, \
please open the port", instant);
please connect to the port", instant);
socket.listen(4321).unwrap();
}

3
examples/tx_stm32f407.rs
View File

@ -57,7 +57,8 @@ fn main() -> ! {
// Create SPI1 for HAL
let spi_eth_port = Spi::spi1(
spi1, (spi1_sck, spi1_miso, spi1_mosi),
enc424j600::spi::SPI_MODE, enc424j600::spi::SPI_CLOCK.into(),
enc424j600::spi::interfaces::SPI_MODE,
enc424j600::spi::interfaces::SPI_CLOCK.into(),
clocks);
let mut spi_eth = enc424j600::SpiEth::new(spi_eth_port, spi1_nss);
// Init

66
src/lib.rs
View File

@ -62,22 +62,22 @@ impl <'c, SPI: Transfer<u8>,
NSS: OutputPin> EthController<'c> for SpiEth<SPI, NSS> {
fn init_dev(&mut self) -> Result<(), EthControllerError> {
// Write 0x1234 to EUDAST
self.spi_port.write_reg_16b(spi::EUDAST, 0x1234)?;
self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?;
// Verify that EUDAST is 0x1234
let mut eudast = self.spi_port.read_reg_16b(spi::EUDAST)?;
let mut eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
if eudast != 0x1234 {
return Err(EthControllerError::GeneralError)
}
// Poll CLKRDY (ESTAT<12>) to check if it is set
loop {
let estat = self.spi_port.read_reg_16b(spi::ESTAT)?;
let estat = self.spi_port.read_reg_16b(spi::addrs::ESTAT)?;
if estat & 0x1000 == 0x1000 { break }
}
// Set ETHRST (ECON2<4>) to 1
let econ2 = self.spi_port.read_reg_8b(spi::ECON2)?;
self.spi_port.write_reg_8b(spi::ECON2, 0x10 | (econ2 & 0b11101111))?;
let econ2 = self.spi_port.read_reg_8b(spi::addrs::ECON2)?;
self.spi_port.write_reg_8b(spi::addrs::ECON2, 0x10 | (econ2 & 0b11101111))?;
// Verify that EUDAST is 0x0000
eudast = self.spi_port.read_reg_16b(spi::EUDAST)?;
eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
if eudast != 0x0000 {
return Err(EthControllerError::GeneralError)
}
@ -86,37 +86,37 @@ impl <'c, SPI: Transfer<u8>,
fn init_rxbuf(&mut self) -> Result<(), EthControllerError> {
// Set ERXST pointer
self.spi_port.write_reg_16b(spi::ERXST, self.rx_buf.get_wrap_addr())?;
self.spi_port.write_reg_16b(spi::addrs::ERXST, self.rx_buf.get_wrap_addr())?;
// Set ERXTAIL pointer
self.spi_port.write_reg_16b(spi::ERXTAIL, self.rx_buf.get_tail_addr())?;
self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, self.rx_buf.get_tail_addr())?;
// Set MAMXFL to maximum number of bytes in each accepted packet
self.spi_port.write_reg_16b(spi::MAMXFL, rx::RAW_FRAME_LENGTH_MAX as u16)?;
self.spi_port.write_reg_16b(spi::addrs::MAMXFL, rx::RAW_FRAME_LENGTH_MAX as u16)?;
// Enable RXEN (ECON1<0>)
let econ1 = self.spi_port.read_reg_16b(spi::ECON1)?;
self.spi_port.write_reg_16b(spi::ECON1, 0x1 | (econ1 & 0xfffe))?;
let econ1 = self.spi_port.read_reg_16b(spi::addrs::ECON1)?;
self.spi_port.write_reg_16b(spi::addrs::ECON1, 0x1 | (econ1 & 0xfffe))?;
Ok(())
}
fn init_txbuf(&mut self) -> Result<(), EthControllerError> {
// Set EGPWRPT pointer
self.spi_port.write_reg_16b(spi::EGPWRPT, 0x0000)?;
self.spi_port.write_reg_16b(spi::addrs::EGPWRPT, 0x0000)?;
Ok(())
}
/// Receive the next packet and copy it to rx_packet_buf
/// Receive the next packet and return it
/// Set is_poll to true for returning until PKTIF is set;
/// Set is_poll to false for returning Err when PKTIF is not set
fn receive_next(&mut self, is_poll: bool) -> Result<rx::RxPacket, EthControllerError> {
// Poll PKTIF (EIR<4>) to check if it is set
loop {
let eir = self.spi_port.read_reg_16b(spi::EIR)?;
let eir = self.spi_port.read_reg_16b(spi::addrs::EIR)?;
if eir & 0x40 == 0x40 { break }
if !is_poll {
return Err(EthControllerError::NoRxPacketError)
}
}
// Set ERXRDPT pointer to next_addr
self.spi_port.write_reg_16b(spi::ERXRDPT, self.rx_buf.get_next_addr())?;
self.spi_port.write_reg_16b(spi::addrs::ERXRDPT, self.rx_buf.get_next_addr())?;
// Read 2 bytes to update next_addr
let mut next_addr_buf = [0; 3];
self.spi_port.read_rxdat(&mut next_addr_buf, 2)?;
@ -136,13 +136,13 @@ impl <'c, SPI: Transfer<u8>,
rx_packet.copy_frame_from(&frame_buf[1..]);
// Set ERXTAIL pointer to (next_addr - 2)
if self.rx_buf.get_next_addr() > rx::ERXST_DEFAULT {
self.spi_port.write_reg_16b(spi::ERXTAIL, self.rx_buf.get_next_addr() - 2)?;
self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, self.rx_buf.get_next_addr() - 2)?;
} else {
self.spi_port.write_reg_16b(spi::ERXTAIL, rx::RX_MAX_ADDRESS - 1)?;
self.spi_port.write_reg_16b(spi::addrs::ERXTAIL, rx::RX_MAX_ADDRESS - 1)?;
}
// Set PKTDEC (ECON1<88>) to decrement PKTCNT
let econ1_hi = self.spi_port.read_reg_8b(spi::ECON1 + 1)?;
self.spi_port.write_reg_8b(spi::ECON1 + 1, 0x01 | (econ1_hi & 0xfe))?;
let econ1_hi = self.spi_port.read_reg_8b(spi::addrs::ECON1 + 1)?;
self.spi_port.write_reg_8b(spi::addrs::ECON1 + 1, 0x01 | (econ1_hi & 0xfe))?;
// Return the RxPacket
Ok(rx_packet)
}
@ -150,22 +150,22 @@ impl <'c, SPI: Transfer<u8>,
/// Send an established packet
fn send_raw_packet(&mut self, packet: &tx::TxPacket) -> Result<(), EthControllerError> {
// Set EGPWRPT pointer to next_addr
self.spi_port.write_reg_16b(spi::EGPWRPT, self.tx_buf.get_next_addr())?;
self.spi_port.write_reg_16b(spi::addrs::EGPWRPT, self.tx_buf.get_next_addr())?;
// Copy packet data to SRAM Buffer
// 1-byte Opcode is included
let mut txdat_buf: [u8; tx::RAW_FRAME_LENGTH_MAX + 1] = [0; tx::RAW_FRAME_LENGTH_MAX + 1];
packet.write_frame_to(&mut txdat_buf[1..]);
self.spi_port.write_txdat(&mut txdat_buf, packet.get_frame_length() as u32)?;
// Set ETXST to packet start address
self.spi_port.write_reg_16b(spi::ETXST, self.tx_buf.get_next_addr())?;
self.spi_port.write_reg_16b(spi::addrs::ETXST, self.tx_buf.get_next_addr())?;
// Set ETXLEN to packet length
self.spi_port.write_reg_16b(spi::ETXLEN, packet.get_frame_length() as u16)?;
self.spi_port.write_reg_16b(spi::addrs::ETXLEN, packet.get_frame_length() as u16)?;
// Set TXRTS (ECON1<1>) to start transmission
let mut econ1_lo = self.spi_port.read_reg_8b(spi::ECON1)?;
self.spi_port.write_reg_8b(spi::ECON1, 0x02 | (econ1_lo & 0xfd))?;
let mut econ1_lo = self.spi_port.read_reg_8b(spi::addrs::ECON1)?;
self.spi_port.write_reg_8b(spi::addrs::ECON1, 0x02 | (econ1_lo & 0xfd))?;
// Poll TXRTS (ECON1<1>) to check if it is reset
loop {
econ1_lo = self.spi_port.read_reg_8b(spi::ECON1)?;
econ1_lo = self.spi_port.read_reg_8b(spi::addrs::ECON1)?;
if econ1_lo & 0x02 == 0x02 { break }
}
// TODO: Read ETXSTAT to understand Ethernet transmission status
@ -181,19 +181,19 @@ impl <'c, SPI: Transfer<u8>,
// From Section 10.12, ENC424J600 Data Sheet:
// "To accept all incoming frames regardless of content (Promiscuous mode),
// set the CRCEN, RUNTEN, UCEN, NOTMEEN and MCEN bits."
let erxfcon_lo = self.spi_port.read_reg_8b(spi::ERXFCON)?;
self.spi_port.write_reg_8b(spi::ERXFCON, 0b0101_1110 | (erxfcon_lo & 0b1010_0001))?;
let erxfcon_lo = self.spi_port.read_reg_8b(spi::addrs::ERXFCON)?;
self.spi_port.write_reg_8b(spi::addrs::ERXFCON, 0b0101_1110 | (erxfcon_lo & 0b1010_0001))?;
Ok(())
}
/// Read MAC to [u8; 6]
fn read_from_mac(&mut self, mac: &mut [u8]) -> Result<(), EthControllerError> {
mac[0] = self.spi_port.read_reg_8b(spi::MAADR1)?;
mac[1] = self.spi_port.read_reg_8b(spi::MAADR1 + 1)?;
mac[2] = self.spi_port.read_reg_8b(spi::MAADR2)?;
mac[3] = self.spi_port.read_reg_8b(spi::MAADR2 + 1)?;
mac[4] = self.spi_port.read_reg_8b(spi::MAADR3)?;
mac[5] = self.spi_port.read_reg_8b(spi::MAADR3 + 1)?;
mac[0] = self.spi_port.read_reg_8b(spi::addrs::MAADR1)?;
mac[1] = self.spi_port.read_reg_8b(spi::addrs::MAADR1 + 1)?;
mac[2] = self.spi_port.read_reg_8b(spi::addrs::MAADR2)?;
mac[3] = self.spi_port.read_reg_8b(spi::addrs::MAADR2 + 1)?;
mac[4] = self.spi_port.read_reg_8b(spi::addrs::MAADR3)?;
mac[5] = self.spi_port.read_reg_8b(spi::addrs::MAADR3 + 1)?;
Ok(())
}
}

30
src/spi.rs
View File

@ -4,14 +4,15 @@ use stm32f4xx_hal::{
blocking::spi::Transfer,
digital::v2::OutputPin,
},
time::MegaHertz,
spi,
};
///
/// FIXME: Move the following to somewhere else
///
use crate::rx;
pub mod interfaces {
use stm32f4xx_hal::{
spi,
time::MegaHertz
};
/// Must use SPI mode cpol=0, cpha=0
pub const SPI_MODE: spi::Mode = spi::Mode {
polarity: spi::Polarity::IdleLow,
@ -19,13 +20,17 @@ pub const SPI_MODE: spi::Mode = spi::Mode {
};
/// Max freq = 14 MHz
pub const SPI_CLOCK: MegaHertz = MegaHertz(14);
}
pub mod opcodes {
/// SPI Opcodes
const RCRU: u8 = 0b0010_0000;
const WCRU: u8 = 0b0010_0010;
const RERXDATA: u8 = 0b0010_1100; // 8-bit opcode followed by data
const WEGPDATA: u8 = 0b0010_1010; // 8-bit opcode followed by data
pub const RCRU: u8 = 0b0010_0000;
pub const WCRU: u8 = 0b0010_0010;
pub const RERXDATA: u8 = 0b0010_1100; // 8-bit opcode followed by data
pub const WEGPDATA: u8 = 0b0010_1010; // 8-bit opcode followed by data
}
pub mod addrs {
/// SPI Register Mapping
/// Note: PSP interface use different address mapping
// SPI Init Reset Registers
@ -50,6 +55,7 @@ pub const EGPWRPT: u8 = 0x88; // 16-bit data
pub const ETXST: u8 = 0x00; // 16-bit data
pub const ETXSTAT: u8 = 0x12; // 16-bit data
pub const ETXLEN: u8 = 0x02; // 16-bit data
}
/// Struct for SPI I/O interface on ENC424J600
/// Note: stm32f4xx_hal::spi's pins include: SCK, MISO, MOSI
@ -77,7 +83,7 @@ impl <SPI: Transfer<u8>,
pub fn read_reg_8b(&mut self, addr: u8) -> Result<u8, SpiPortError> {
// Using RCRU instruction to read using unbanked (full) address
let mut r_data = self.rw_addr_u8(RCRU, addr, 0)?;
let mut r_data = self.rw_addr_u8(opcodes::RCRU, addr, 0)?;
Ok(r_data)
}
@ -91,7 +97,7 @@ impl <SPI: Transfer<u8>,
// Currently requires manual slicing (buf[1..]) for the data read back
pub fn read_rxdat<'a>(&mut self, buf: &'a mut [u8], data_length: u32)
-> Result<(), SpiPortError> {
let r_valid = self.r_n(buf, RERXDATA, data_length)?;
let r_valid = self.r_n(buf, opcodes::RERXDATA, data_length)?;
Ok(r_valid)
}
@ -99,14 +105,14 @@ impl <SPI: Transfer<u8>,
// TODO: Maybe better naming?
pub fn write_txdat<'a>(&mut self, buf: &'a mut [u8], data_length: u32)
-> Result<(), SpiPortError> {
let w_valid = self.w_n(buf, WEGPDATA, data_length)?;
let w_valid = self.w_n(buf, opcodes::WEGPDATA, data_length)?;
Ok(w_valid)
}
pub fn write_reg_8b(&mut self, addr: u8, data: u8) -> Result<(), SpiPortError> {
// TODO: addr should be separated from w_data
// Using WCRU instruction to write using unbanked (full) address
self.rw_addr_u8(WCRU, addr, data)?;
self.rw_addr_u8(opcodes::WCRU, addr, data)?;
Ok(())
}