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examples: Clarify SPI clock selection

This commit is contained in:
Harry Ho 2021-07-29 17:37:12 +08:00
parent 512fd154bd
commit 2da2a91572
2 changed files with 4 additions and 6 deletions
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4
examples/tcp_stm32f407.rs
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@ -117,7 +117,7 @@ const APP: () = {
.cfgr .cfgr
.sysclk(168.mhz()) .sysclk(168.mhz())
.hclk(168.mhz()) .hclk(168.mhz())
.pclk1(42.mhz()) .pclk2(42.mhz()) // used by SPI1
.require_pll48clk() .require_pll48clk()
.freeze(); .freeze();
let mut delay = Delay::new(c.core.SYST, clocks); let mut delay = Delay::new(c.core.SYST, clocks);
@ -149,7 +149,7 @@ const APP: () = {
let spi_eth_port = Spi::spi1( let spi_eth_port = Spi::spi1(
spi1, (spi1_sck, spi1_miso, spi1_mosi), spi1, (spi1_sck, spi1_miso, spi1_mosi),
enc424j600::spi::interfaces::SPI_MODE, enc424j600::spi::interfaces::SPI_MODE,
Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ), 10_500_000.hz(), // PCLK2 @ 42MHz, set SPI1 baud rate as f_PCLK2 divided by 4
clocks); clocks);
SpiEth::new(spi_eth_port, spi1_nss) SpiEth::new(spi_eth_port, spi1_nss)

6
examples/tx_stm32f407.rs
View File

@ -49,9 +49,7 @@ const APP: () = {
.cfgr .cfgr
.sysclk(168.mhz()) .sysclk(168.mhz())
.hclk(168.mhz()) .hclk(168.mhz())
//.pclk1(32.mhz()) .pclk2(42.mhz()) // used by SPI1
.pclk1(42.mhz())
//.pclk2(64.mhz())
.require_pll48clk() .require_pll48clk()
.freeze(); .freeze();
let mut delay = Delay::new(c.core.SYST, clocks); let mut delay = Delay::new(c.core.SYST, clocks);
@ -80,7 +78,7 @@ const APP: () = {
let spi_eth_port = Spi::spi1( let spi_eth_port = Spi::spi1(
spi1, (spi1_sck, spi1_miso, spi1_mosi), spi1, (spi1_sck, spi1_miso, spi1_mosi),
enc424j600::spi::interfaces::SPI_MODE, enc424j600::spi::interfaces::SPI_MODE,
Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ), 10_500_000.hz(), // PCLK2 @ 42MHz, set SPI1 baud rate as f_PCLK2 divided by 4
clocks); clocks);
SpiEth::new(spi_eth_port, spi1_nss) SpiEth::new(spi_eth_port, spi1_nss)