forked from M-Labs/artiq
Robert Jordens
8adef12781
* remove rt2wb_output * remove ttl_*() ttl.c ttl.h * use rtio_output() and rtio_input_timestamp() * adapt coredevice/compiler layer * adapt bridge to not artiq_raise_from_c()
14 lines
405 B
Python
14 lines
405 B
Python
from artiq.language.core import syscall
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from artiq.language.types import TInt64, TInt32, TNone
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@syscall
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def rtio_output(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32
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) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall
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def rtio_input_timestamp(timeout_mu: TInt64, channel: TInt32) -> TInt64:
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raise NotImplementedError("syscall not simulated")
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