forked from M-Labs/artiq
den512
93882eb3ce
Change initialization behaviour of GTX transceivers -- Modify the config parms CPLL of GTX transceiver for PLL to lock correctly Modify the enabling requirement of GTX input clock buffer IBUFDS_GTE2 so that it depends on GTX PLL locked signal instead of TX Init Done Modify the GTX Init FSM so that BruteForceClock Aligner can reset GTX transceiver without resetting the GTX transceiver PLL kasli-soc: fix of SYS CLK switch failure Changed initialization of GTX transceivers. Successful SYS CLK switching requires IBUFDS_GTE2 to be properly enabled and not disabled during GTX transceiver initialization. For this reason, CPLL is not reset during GTX initialization and clock alignment. kasli-soc: refractor fix of SYS CLK switch failure Remove gtXxreset & cpllreset assertion and deassertion The removed code does not affect the fix |
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.. | ||
applets | ||
browser | ||
compiler | ||
coredevice | ||
dashboard | ||
examples | ||
firmware | ||
frontend | ||
gateware | ||
gui | ||
language | ||
master | ||
sim | ||
test | ||
wavesynth | ||
__init__.py | ||
_version.py | ||
appdirs.py | ||
build_soc.py | ||
experiment.py | ||
remoting.py | ||
tools.py |