forked from M-Labs/artiq
Robert Jordens
4a0eaf0f95
gateware: add jesd204b awg gateware: copy phaser (df3825a) dsp/tools: update satadd mixin phaser: no DDS stubs dsp: accu fix phaser: cleanup/reduce sawg: kernel support and docs sawg: coredevice api fixes sawg: example ddb/experiment phaser: add conda package examples/phaser: typo sawg: adapt tests, fix accu stb sawg: tweak dds parameters sawg: move/adapt/extend tests sawg: test phy, refactor phaser: non-rtio spi phaser: target cli update phaser: ad9154-fmc-ebz pins phaser: reorganize fmc signal naming phaser: add test mode stubs phaser: txen is LVTTL phaser: clk spi xfer test phaser: spi for ad9154 and ad9516 phaser: spi tweaks ad9154: add register map from ad9144.xml ad9516: add register map from ad9517.xml and manual adaptation ad9154_reg: just generate getter/setter macros as well ad9154: reg WIP ad9154: check and fix registers kc705: single ended rtio_external_clk use single ended user_sma_clk_n instead of p/n to free up one clock sma kc705: mirror clk200 at user_sma_clock_p ad9516_regs.h: fix B_COUNTER_MSB phase: wire up clocking differently needs patched misoc kc705: feed rtio_external_clock directly kc705: remove rtio_external_clk for phaser phaser: spi tweaks ad9516: some startup ad9516_reg fixes phaser: setup ad9516 for supposed 500 MHz operation ad9516: use full duplex spi ad9154_reg: add CONFIG_REG_2 ad9154_reg: fixes phaser: write some ad9154 config ad9154_reg: fixes ad9154: more init, and human readable setup ad9154/ad9516: merge spi support ad9154: status readout Revert "kc705: remove rtio_external_clk for phaser" This reverts commit d500288bb44f2bf2eeb0c2f237aa207b0a8b1366. Revert "kc705: feed rtio_external_clock directly" This reverts commit 8dc7825519e3e75b7d3d29c9abf10fc6e3a8b4c5. Revert "phase: wire up clocking differently" This reverts commit ad9cc450ffa35abb54b0842d56f6cf6c53c6fbcc. Revert "kc705: mirror clk200 at user_sma_clock_p" This reverts commit 7f0dffdcdd28e648af84725682f82ec6e5642eba. Revert "kc705: single ended rtio_external_clk" This reverts commit a9426d983fbf5c1cb768da8f1da26d9b7335e9cf. ad9516: 2000 MHz clock phaser: test clock dist phaser: test freqs ad9154: iostandards phaser: drop clock monitor phaser: no separate i2c phaser: drive rtio from refclk, wire up sysref phaser: ttl channel for sync ad9154: 4x interp, status, tweaks phaser: sync/sysref 33V banks phaser: sync/sysref LVDS_25 inputs are VCCO tolerant phaser: user input-only ttls phaser: rtio fully from refclk ad9154: reg name usage fix ad9154: check register modifications Revert "ad9154: check register modifications" This reverts commit 45121d90edf89f7bd8703503f9f317ad050f9564. ad9154: fix status code ad9154: addrinc, recal serdes pll phaser: coredevice, example tweaks sawg: missing import sawg: type fixes ad9514: move setup functions ad9154: msb first also decreasing addr phaser: use sys4x for rtio internal ref phaser: move init code to main phaser: naming cleanup phaser: cleanup pins phaser: move spi to kernel cpu phaser: kernel support for ad9154 spi ad9154: add r/w methods ad9154: need return annotations ad9154: r/w methods are kernels ad9154_reg: portable helpers phaser: cleanup startup kernel ad9154: status test ad9154: prbs test ad9154: move setup, document phaser: more documentation
239 lines
12 KiB
ReStructuredText
239 lines
12 KiB
ReStructuredText
Core device
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===========
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The core device is a FPGA-based hardware component that contains a softcore CPU tightly coupled with the so-called RTIO core that provides precision timing. The CPU executes Python code that is statically compiled by the ARTIQ compiler, and communicates with the core device peripherals (TTL, DDS, etc.) over the RTIO core. This architecture provides high timing resolution, low latency, low jitter, high level programming capabilities, and good integration with the rest of the Python experiment code.
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While it is possible to use all the other parts of ARTIQ (controllers, master, GUI, dataset management, etc.) without a core device, many experiments require it.
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.. _core-device-flash-storage:
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Flash storage
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*************
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The core device contains some flash space that can be used to store configuration data.
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This storage area is used to store the core device MAC address, IP address and even the idle kernel.
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The flash storage area is one sector (typically 64 kB) large and is organized as a list of key-value records.
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This flash storage space can be accessed by using ``artiq_coreconfig`` (see: :ref:`core-device-configuration-tool`).
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.. _board-ports:
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FPGA board ports
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****************
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All boards have a serial interface running at 115200bps 8-N-1 that can be used for debugging.
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KC705
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-----
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The main target board for the ARTIQ core device is the KC705 development board from Xilinx. It supports the NIST QC1 hardware via an adapter, and the NIST CLOCK and QC2 hardware (FMC).
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Common problems
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+++++++++++++++
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* The SW13 switches on the board need to be set to 00001.
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* When connected, QC1 and CLOCK adapters break the JTAG chain due to TDI not being connect to TDO on the FMC mezzanine.
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* On some boards, the JTAG USB connector is not correctly soldered.
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VADJ
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++++
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With the NIST CLOCK and QC2 adapters, for safe operation of the DDS buses (to prevent damage to the IO banks of the FPGA), the FMC VADJ rail of the KC705 should be changed to 3.3V. Plug the Texas Instruments USB-TO-GPIO PMBus adapter into the PMBus connector in the corner of the KC705 and use the Fusion Digital Power Designer software to configure (requires Windows). Write to chip number U55 (address 52), channel 4, which is the VADJ rail, to make it 3.3V instead of 2.5V. Power cycle the KC705 board to check that the startup voltage on the VADJ rail is now 3.3V.
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NIST QC1
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++++++++
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With the QC1 hardware, the TTL lines are mapped as follows:
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+--------------+------------+--------------+
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| RTIO channel | TTL line | Capability |
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+==============+============+==============+
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| 0 | PMT0 | Input |
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+--------------+------------+--------------+
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| 1 | PMT1 | Input |
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+--------------+------------+--------------+
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| 2-16 | TTL0-14 | Output |
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+--------------+------------+--------------+
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| 17 | SMA_GPIO_N | Input+Output |
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+--------------+------------+--------------+
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| 18 | LED | Output |
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+--------------+------------+--------------+
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| 19 | TTL15 | Clock |
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+--------------+------------+--------------+
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There are no SPI channels.
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The DDS bus is on channel 20.
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NIST CLOCK
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++++++++++
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With the CLOCK hardware, the TTL lines are mapped as follows:
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+--------------------+-----------------------+--------------+
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| RTIO channel | TTL line | Capability |
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+====================+=======================+==============+
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| 3,7,11,15 | TTL3,7,11,15 | Input+Output |
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+--------------------+-----------------------+--------------+
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| 0-2,4-6,8-10,12-14 | TTL0-2,4-6,8-10,12-14 | Output |
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+--------------------+-----------------------+--------------+
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| 16 | PMT0 | Input |
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+--------------------+-----------------------+--------------+
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| 17 | PMT1 | Input |
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+--------------------+-----------------------+--------------+
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| 18 | SMA_GPIO_N | Input+Output |
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+--------------------+-----------------------+--------------+
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| 19 | LED | Output |
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+--------------------+-----------------------+--------------+
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| 20 | AMS101_LDAC_B | Output |
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+--------------------+-----------------------+--------------+
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| 21 | LA32_P | Clock |
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+--------------------+-----------------------+--------------+
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The board has RTIO SPI buses mapped as follows:
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+--------------+-------------+-------------+-----------+------------+
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| RTIO channel | CS_N | MOSI | MISO | CLK |
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+==============+=============+=============+===========+============+
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| 22 | AMS101_CS_N | AMS101_MOSI | | AMS101_CLK |
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+--------------+-------------+-------------+-----------+------------+
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| 23 | SPI0_CS_N | SPI0_MOSI | SPI0_MISO | SPI0_CLK |
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+--------------+-------------+-------------+-----------+------------+
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| 24 | SPI1_CS_N | SPI1_MOSI | SPI1_MISO | SPI1_CLK |
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+--------------+-------------+-------------+-----------+------------+
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| 25 | SPI2_CS_N | SPI2_MOSI | SPI2_MISO | SPI2_CLK |
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+--------------+-------------+-------------+-----------+------------+
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The DDS bus is on channel 26.
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NIST QC2
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++++++++
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With the QC2 hardware, the TTL lines are mapped as follows:
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+--------------------+-----------------------+--------------+
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| RTIO channel | TTL line | Capability |
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+====================+=======================+==============+
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| 0-39 | TTL0-39 | Input+Output |
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+--------------------+-----------------------+--------------+
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| 40 | SMA_GPIO_N | Input+Output |
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+--------------------+-----------------------+--------------+
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| 41 | LED | Output |
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+--------------------+-----------------------+--------------+
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| 42 | AMS101_LDAC_B | Output |
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+--------------------+-----------------------+--------------+
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| 43, 44 | CLK0, CLK1 | Clock |
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+--------------------+-----------------------+--------------+
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The board has RTIO SPI buses mapped as follows:
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+--------------+-------------+-------------+-----------+------------+
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| RTIO channel | CS_N | MOSI | MISO | CLK |
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+==============+=============+=============+===========+============+
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| 45 | AMS101_CS_N | AMS101_MOSI | | AMS101_CLK |
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+--------------+-------------+-------------+-----------+------------+
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| 46 | SPI0_CS_N | SPI0_MOSI | SPI0_MISO | SPI0_CLK |
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+--------------+-------------+-------------+-----------+------------+
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| 47 | SPI1_CS_N | SPI1_MOSI | SPI1_MISO | SPI1_CLK |
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+--------------+-------------+-------------+-----------+------------+
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| 48 | SPI2_CS_N | SPI2_MOSI | SPI2_MISO | SPI2_CLK |
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+--------------+-------------+-------------+-----------+------------+
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| 49 | SPI3_CS_N | SPI3_MOSI | SPI3_MISO | SPI3_CLK |
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+--------------+-------------+-------------+-----------+------------+
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There are two DDS buses on channels 50 (LPC, DDS0-DDS11) and 51 (HPC, DDS12-DDS23).
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The QC2 hardware uses TCA6424A I2C I/O expanders to define the directions of its TTL buffers. There is one such expander per FMC card, and they are selected using the PCA9548 on the KC705.
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To avoid I/O contention, the startup kernel should first program the TCA6424A expanders and then call ``output()`` on all ``TTLInOut`` channels that should be configured as outputs.
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See :mod:`artiq.coredevice.i2c` for more details.
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Phaser
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++++++
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The Phaser adapter is an AD9154-FMC-EBZ, a 4 channel 2.4 GHz DAC on an FMC HPC card.
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+--------------+------------+--------------+
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| RTIO channel | TTL line | Capability |
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+==============+============+==============+
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| 0 | SMA_GPIO_N | Input+Output |
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+--------------+------------+--------------+
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| 1 | LED | Output |
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+--------------+------------+--------------+
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| 2 | SYSREF | Input |
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+--------------+------------+--------------+
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| 3 | SYNC | Input |
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+--------------+------------+--------------+
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The SAWG channels start with RTIO channel number 4, each occupying 3 channels.
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The board has one non-RTIO SPI bus that is accessible through
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:mod:`artiq.coredevice.ad9154`.
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* Setup the KC705 observing the notes above and as laid out in :ref:`configuring-core-device`.
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* A 2 GHz of roughly 10 dBm (0.2 to 3.4 V peak-to-peak into 50 Ohm) must be connected to the AD9154-FMC-EBZ J1.
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The external RTIO clock, DAC deviceclock, FPGA deviceclock, and SYSREF are derived from this signal.
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* The ``startup_clock`` needs to be set to internal (``i``) for bootstrapping the clock distribution tree.
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See :ref:`configuring-core-device`.
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* Compile and flash the startup kernel in ``artiq/examples/phaser/startup_kernel.py``.
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* An example ``device_db.pyon`` is provided in ``artiq/examples/phaser/device_db.pyon``.
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Pipistrello
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-----------
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The low-cost Pipistrello FPGA board can be used as a lower-cost but slower alternative. Since the device does not have a native network interface, a PPP session is run over the serial port (which is then run over USB). To establish the PPP session with the core device, giving it the IP address 10.0.0.2, as root execute::
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pppd /dev/ttyUSB1 115200 noauth nodetach local nocrtscts novj 10.0.0.1:10.0.0.2
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.. warning:: Windows is not supported.
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.. warning:: The Pipistrello draws a high current over USB, and that current increases when the FPGA design is active. If you experience problems such as intermittent board freezes or USB errors, try connecting it to a self-powered USB hub.
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When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are mapped to RTIO channels as follows:
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+--------------+------------+--------------+
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| RTIO channel | TTL line | Capability |
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+==============+============+==============+
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| 0 | PMT0 | Input |
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+--------------+------------+--------------+
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| 1 | PMT1 | Input |
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+--------------+------------+--------------+
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| 2-16 | TTL0-14 | Output |
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+--------------+------------+--------------+
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| 17 | EXT_LED | Output |
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+--------------+------------+--------------+
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| 18 | USER_LED_1 | Output |
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+--------------+------------+--------------+
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| 19 | USER_LED_2 | Output |
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+--------------+------------+--------------+
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| 20 | USER_LED_3 | Output |
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+--------------+------------+--------------+
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| 21 | USER_LED_4 | Output |
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+--------------+------------+--------------+
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| 22 | TTL15 | Clock |
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+--------------+------------+--------------+
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The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Pipistrello board), the corresponding pins on the Pipistrello can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention.
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The board can accept an external RTIO clock connected to PMT2. If the DDS box does not drive the PMT2 pair, use XTRIG and patch the XTRIG transceiver output on the adapter board onto C:15 disconnecting PMT2.
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The board has one RTIO SPI bus on the PMOD connector, compliant to PMOD
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Interface Type 2 (SPI) and 2A (expanded SPI):
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+--------------+--------+--------+--------+--------+
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| RTIO channel | CS_N | MOSI | MISO | CLK |
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+==============+========+========+========+========+
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| 23 | PMOD_0 | PMOD_1 | PMOD_2 | PMOD_3 |
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+--------------+--------+--------+--------+--------+
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The DDS bus is on channel 24.
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