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forked from M-Labs/artiq
artiq/artiq/gateware/drtio
2018-05-12 22:57:11 +08:00
..
transceiver drtio/gth: power down rx on restart (seems to make link initialization reliable) 2018-03-06 11:49:28 +01:00
__init__.py drtio: structure 2016-10-10 23:12:12 +08:00
aux_controller.py drtio: implement inputs in RTPacketSatellite, reorganize code 2017-03-07 00:46:59 +08:00
core.py drtio: fix satellite minimum_coarse_timestamp clock domain (#947) 2018-03-13 00:20:57 +08:00
link_layer.py drtio: raise RTIOLinkError if operation fails due to link lost (#942) 2018-03-04 01:02:53 +08:00
rt_controller_master.py drtio: remove TSC correction (#40) 2018-03-09 10:36:17 +08:00
rt_errors_satellite.py drtio: print diagnostic info on satellite write underflow (#947) 2018-03-12 23:41:19 +08:00
rt_packet_master.py drtio: rewrite/fix reset and link bringup/teardown 2018-02-20 17:26:43 +08:00
rt_packet_satellite.py drtio: rewrite/fix reset and link bringup/teardown 2018-02-20 17:26:43 +08:00
rt_serializer.py drtio: rewrite/fix reset and link bringup/teardown 2018-02-20 17:26:43 +08:00
rx_synchronizer.py drtio: reorganize RX synchronizers 2018-02-22 15:21:23 +08:00
siphaser.py siphaser: support external reference for the freerunning 150MHz 2018-05-12 22:57:11 +08:00