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forked from M-Labs/artiq
artiq/artiq/gateware/drtio
2017-03-27 16:32:23 +08:00
..
transceiver drtio: add false paths between sys and transceiver clocks 2016-12-03 23:03:01 +08:00
__init__.py drtio: structure 2016-10-10 23:12:12 +08:00
aux_controller.py drtio: implement inputs in RTPacketSatellite, reorganize code 2017-03-07 00:46:59 +08:00
core.py drtio: implement inputs in RTPacketSatellite, reorganize code 2017-03-07 00:46:59 +08:00
link_layer.py drtio: implement inputs in RTPacketSatellite, reorganize code 2017-03-07 00:46:59 +08:00
rt_controller_master.py make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads 2017-03-27 16:32:23 +08:00
rt_ios_satellite.py drtio: input fixes 2017-03-14 14:14:43 +08:00
rt_packet_master.py drtio: input support (untested) 2017-03-13 23:54:44 +08:00
rt_packet_satellite.py drtio: input support (untested) 2017-03-13 23:54:44 +08:00
rt_serializer.py drtio: input support (untested) 2017-03-13 23:54:44 +08:00