forked from M-Labs/artiq
morgan
bd1759dbf9
core: add ROICropper to crop the ROI for downstream consumption core: add ROIViewer to buffer the cropped pixels rtio: connect pixel source to ROIViewer
353 lines
12 KiB
Python
353 lines
12 KiB
Python
from migen import *
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from misoc.interconnect.csr import *
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from misoc.interconnect.stream import AsyncFIFO, Buffer, Endpoint, SyncFIFO
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from misoc.cores.coaxpress.common import char_width, word_layout_dchar, word_width
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from misoc.cores.coaxpress.core import HostTXCore, HostRXCore
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from misoc.cores.coaxpress.core.packet import StreamPacketArbiter
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from misoc.cores.coaxpress.core.crc import CXPCRC32Checker
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from artiq.gateware.cxp_grabber.frame import (
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EndOfLineMarker,
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FrameHeaderReader,
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PixelParser,
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pixelword_layout,
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)
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from operator import or_, add
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class CXPHostCore(Module, AutoCSR):
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def __init__(self, tx_phy, rx_phy, clk_freq, command_buffer_depth=32, nrxslot=4):
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# control buffer is only 32 words (128 bytes) wide for compatibility with CXP 1.x compliant devices
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# Section 12.1.6 (CXP-001-2021)
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self.buffer_depth, self.nslots = command_buffer_depth, nrxslot
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self.submodules.tx = HostTXCore(tx_phy, command_buffer_depth, clk_freq, False)
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self.submodules.rx = HostRXCore(rx_phy, command_buffer_depth, nrxslot, False)
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def get_tx_port(self):
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return self.tx.writer.mem.get_port(write_capable=True)
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def get_rx_port(self):
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return self.rx.command_reader.mem.get_port(write_capable=False)
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def get_mem_size(self):
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return word_width * self.buffer_depth * self.nslots // 8
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class StreamDecoder(Module, AutoCSR):
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"""
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Convert the raw frame data into pixel data
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Currently only support:
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- Pixel format: mono8, mono10, mono12, mono14, mono16
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- Tap geometry: 1X-1Y
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- Scanning mode: area scanning
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"""
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def __init__(self, res_width):
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self.crc_error = CSR()
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self.stream_type_error = CSR()
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self.new_frame = CSR()
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self.x_size = CSRStatus(3*char_width)
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self.y_size = CSRStatus(3*char_width)
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self.pixel_format_code = CSRStatus(2*char_width)
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# # #
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cdr = ClockDomainsRenamer("cxp_gt_rx")
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#
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# 32+8(dchar) 32
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# sink ────/────> stream ────> buffer ────> crc checker ─────> frame header ───/───> end of line ─────> skid buffer ─────> pixel parser ─────> 4x pixel with
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# arbiter reader reader marker xy coordinate
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#
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# Drops the packet header & K29.7 and mark eop on the crc word
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self.submodules.arbiter = arbiter = cdr(StreamPacketArbiter())
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# Buffer to improve timing
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self.submodules.buffer = buffer = cdr(Buffer(word_layout_dchar))
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# CRC
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self.submodules.crc_checker = crc_checker = cdr(CXPCRC32Checker())
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self.submodules.crc_error_ps = crc_error_ps = PulseSynchronizer("cxp_gt_rx", "sys")
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self.sync.cxp_gt_rx += crc_error_ps.i.eq(crc_checker.error)
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self.sync += [
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If(crc_error_ps.o,
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self.crc_error.w.eq(1),
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).Elif(self.crc_error.re,
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self.crc_error.w.eq(0),
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),
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]
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# Frame header extraction
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self.submodules.header_reader = header_reader = cdr(FrameHeaderReader())
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# New frame and stream type error notification
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self.submodules.new_frame_ps = new_frame_ps = PulseSynchronizer("cxp_gt_rx", "sys")
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self.submodules.stream_type_err_ps = stream_type_err_ps = PulseSynchronizer("cxp_gt_rx", "sys")
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self.sync.cxp_gt_rx += [
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new_frame_ps.i.eq(header_reader.new_frame),
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stream_type_err_ps.i.eq(header_reader.decode_err),
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]
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self.sync += [
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If(new_frame_ps.o,
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self.new_frame.w.eq(1),
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).Elif(self.new_frame.re,
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self.new_frame.w.eq(0),
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),
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If(stream_type_err_ps.o,
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self.stream_type_error.w.eq(1),
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).Elif(self.stream_type_error.re,
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self.stream_type_error.w.eq(0),
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)
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]
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frame_header = header_reader.header
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self.specials += [
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MultiReg(frame_header.Xsize, self.x_size.status),
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MultiReg(frame_header.Ysize, self.y_size.status),
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MultiReg(frame_header.PixelF, self.pixel_format_code.status),
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]
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# Mark end of line for pixel parser
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self.submodules.eol_marker = eol_marker = cdr(EndOfLineMarker())
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self.sync.cxp_gt_rx += eol_marker.words_per_img_line.eq(frame_header.DsizeL)
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# Skid buffer to prevent pipeline stalling
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# At each linebreak, `Pixel_Parser.sink.ack` will fall for 1-2 cycle.
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# Without the skid buffer , the whole pipleline will stall during that 1-2 cycle.
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#
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# Due to the backpressure, 2 words line marker (4x K28.3 + 4x 0x02) will arrive as the linebreak indicator and will be consumed by `frame_header_reader`
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# Thus, the buffer won't experience any data buildup.
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self.submodules.skid_buf = skid_buf = cdr(SyncFIFO(pixelword_layout, 2))
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self.submodules.parser = parser = cdr(PixelParser(res_width))
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self.sync.cxp_gt_rx += [
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parser.x_size.eq(frame_header.Xsize),
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parser.y_size.eq(frame_header.Ysize),
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parser.pixel_format_code.eq(frame_header.PixelF),
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]
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# Connecting the pipeline
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self.sink = arbiter.sink
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self.comb += arbiter.sources[0].connect(buffer.sink)
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self.pipeline = [buffer, crc_checker, header_reader, eol_marker, skid_buf, parser]
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for s, d in zip(self.pipeline, self.pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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# For downstream ROI engine
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self.source_pixel4x = parser.source_pixel4x
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class ROI(Module):
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"""
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ROI Engine that accept 4 pixels each cycle. For each frame, accumulates pixels values within a
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rectangular region of interest, and reports the total.
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"""
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def __init__(self, pixel_4x, count_width):
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assert len(pixel_4x) == 4
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self.cfg = Record([
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("x0", len(pixel_4x[0].x)),
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("y0", len(pixel_4x[0].y)),
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("x1", len(pixel_4x[0].x)),
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("y1", len(pixel_4x[0].y)),
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])
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self.out = Record([
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("update", 1),
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# registered output - can be used as CDC input
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("count", count_width),
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])
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# # #
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roi_4x = [
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Record([
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("x_good", 1),
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("y_good", 1),
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("gray", len(pixel_4x[0].gray)),
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("stb", 1),
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("count", count_width),
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]) for _ in range(4)
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]
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for pix, roi in zip(pixel_4x, roi_4x):
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self.sync += [
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# stage 1 - generate "good" (in-ROI) signals
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roi.x_good.eq(0),
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If((self.cfg.x0 <= pix.x) & (pix.x < self.cfg.x1),
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roi.x_good.eq(1)
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),
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# the 4 pixels are on the same y level, no need for extra calculation
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If(pix.y == self.cfg.y0,
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roi.y_good.eq(1)
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),
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If(pix.y == self.cfg.y1,
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roi.y_good.eq(0)
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),
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If(pix.eof,
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roi.x_good.eq(0),
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roi.y_good.eq(0)
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),
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roi.gray.eq(pix.gray),
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roi.stb.eq(pix.stb),
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# stage 2 - accumulate
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If((roi.stb & roi.x_good & roi.y_good),
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roi.count.eq(roi.count + roi.gray)
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)
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]
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eof = Signal()
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eof_buf = Signal()
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count_buf = [Signal(count_width), Signal(count_width)]
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# stage 3 - update
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self.sync += [
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eof.eq(reduce(or_, [pix.eof for pix in pixel_4x])),
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eof_buf.eq(eof),
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count_buf[0].eq(roi_4x[0].count + roi_4x[1].count),
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count_buf[1].eq(roi_4x[2].count + roi_4x[3].count),
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self.out.update.eq(0),
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If(eof_buf,
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[roi.count.eq(0) for roi in roi_4x],
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self.out.update.eq(1),
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self.out.count.eq(reduce(add, count_buf))
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),
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]
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class ROICropper(Module):
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def __init__(self, pixel_4x):
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self.enable = Signal()
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self.cfg = Record([
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("x0", len(pixel_4x[0].x)),
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("y0", len(pixel_4x[0].y)),
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("x1", len(pixel_4x[0].x)),
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("y1", len(pixel_4x[0].y)),
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])
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max_pixel_width = len(pixel_4x[0].gray)
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self.source = Endpoint([("data", 4 * max_pixel_width)])
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# # #
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roi_4x = [
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Record([
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("x_good", 1),
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("y_good", 1),
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("gray", max_pixel_width),
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("stb", 1),
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("eof", 1),
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]) for _ in range(4)
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]
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for i, (pix, roi) in enumerate(zip(pixel_4x, roi_4x)):
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self.sync += [
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roi.x_good.eq(0),
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If((self.cfg.x0 <= pix.x) & (pix.x < self.cfg.x1),
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roi.x_good.eq(1)
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),
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# the 4 pixels are on the same y level, no need for extra calculation
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If(pix.y == self.cfg.y0,
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roi.y_good.eq(1)
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),
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If(pix.y == self.cfg.y1,
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roi.y_good.eq(0)
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),
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If(pix.eof,
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roi.x_good.eq(0),
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roi.y_good.eq(0)
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),
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roi.gray.eq(pix.gray),
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roi.stb.eq(pix.stb),
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roi.eof.eq(pix.eof),
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self.source.data[i * max_pixel_width: (i + 1) * max_pixel_width].eq(0),
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If((self.enable & roi.stb & roi.x_good & roi.y_good),
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self.source.data[i * max_pixel_width: (i + 1) * max_pixel_width].eq(roi.gray)
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),
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]
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# use the first roi for flow control as the first pixel is always available
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if i == 0:
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self.sync += [
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self.source.stb.eq(0),
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self.source.eop.eq(0),
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If((self.enable & roi.stb & roi.x_good & roi.y_good),
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self.source.stb.eq(roi.stb),
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self.source.eop.eq(roi.eof),
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),
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]
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class ROIViewer(Module, AutoCSR):
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def __init__(self, pixel_4x, fifo_depth=1024):
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self.arm = CSR()
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self.ready = CSR()
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self.x0 = CSRStorage(len(pixel_4x[0].x))
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self.x1 = CSRStorage(len(pixel_4x[0].y))
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self.y0 = CSRStorage(len(pixel_4x[0].x))
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self.y1 = CSRStorage(len(pixel_4x[0].y))
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max_pixel_width = len(pixel_4x[0].gray)
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self.fifo_ack = CSR()
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self.fifo_data = CSRStatus(4 * max_pixel_width)
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self.fifo_stb = CSRStatus()
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# # #
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cdr = ClockDomainsRenamer("cxp_gt_rx")
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self.submodules.cropper = cropper = cdr(ROICropper(pixel_4x))
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self.submodules.arm_ps = arm_ps = PulseSynchronizer("sys", "cxp_gt_rx")
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self.submodules.ready_ps = ready_ps = PulseSynchronizer("cxp_gt_rx", "sys")
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self.sync += [
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arm_ps.i.eq(self.arm.re),
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If(ready_ps.o,
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self.ready.w.eq(1),
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).Elif(self.ready.re,
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self.ready.w.eq(0),
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),
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]
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self.sync.cxp_gt_rx += [
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If(arm_ps.o,
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cropper.enable.eq(1),
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).Elif(pixel_4x[0].eof,
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cropper.enable.eq(0),
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),
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ready_ps.i.eq(pixel_4x[0].eof),
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]
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self.specials += [
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MultiReg(self.x0.storage, cropper.cfg.x0, "cxp_gt_rx"),
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MultiReg(self.x1.storage, cropper.cfg.x1, "cxp_gt_rx"),
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MultiReg(self.y0.storage, cropper.cfg.y0, "cxp_gt_rx"),
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MultiReg(self.y1.storage, cropper.cfg.y1, "cxp_gt_rx"),
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]
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self.submodules.buffer = buffer = cdr(Buffer([("data", 4 * max_pixel_width)]))
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self.submodules.fifo = fifo = ClockDomainsRenamer(
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{"write": "cxp_gt_rx", "read": "sys"}
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)(AsyncFIFO([("data", 4 * max_pixel_width)], fifo_depth))
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pipeline = [cropper, buffer, fifo]
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for s, d in zip(pipeline, pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.sync += [
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fifo.source.ack.eq(self.fifo_ack.re),
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self.fifo_data.status.eq(fifo.source.data),
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self.fifo_stb.status.eq(fifo.source.stb),
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]
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