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746 Commits

Author SHA1 Message Date
Etienne Wodey
ecef5661ce coredevice/phaser: fix typos in docstring
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2020-10-29 20:27:08 +01:00
eecd97ce4c phaser: debug and comments 2020-09-27 17:15:16 +00:00
c453c24fb0 phaser: tweak slacks 2020-09-26 21:16:08 +00:00
6c8bddcf8d phaser: tune sync_dly 2020-09-26 21:13:00 +00:00
569e5e56cd phaser: autotune and fix fifo_offset 2020-09-26 20:37:16 +00:00
2fba3cfc78 phaser: debug init, systematic bring-up 2020-09-25 20:54:59 +00:00
fec2f8b763 phaser: increase slack for iotest 2020-09-24 10:59:22 +00:00
6e6480ec21 phaser: tweak slacks and errors, identify trf 2020-09-24 08:38:30 +00:00
03d5f985f8 phaser: another artiq-python signed integer quirk 2020-09-23 15:40:54 +00:00
ef65ee18bd dac34h84: unflip spectrum, clear nco 2020-09-23 08:35:56 +00:00
50b4eb4840 Merge branch 'master' into phaser
* master: (26 commits)
  fastino: documentation and eem pass-through
  kasli2: forward sma_clkin to si5324
  test: relax test_dma_playback_time on Zynq
  rpc: fixed _write_bool
  fastino: document/cleanup
  build_soc: remove assertion that was used for test runs
  metlino_sayma_ttl: Fix RTIO frequency & demo code (#1516)
  Revert "test: temporarily disable test_async_throughput"
  build_soc: rename identifier_str to gateware_identifier_str
  test: relax loopback gate timing
  test: temporarily disable test_async_throughput
  test: relax test_pulse_rate on Zynq
  test: skip NonexistentI2CBus if I2C is not supported
  build_soc: override identifier_str only for gateware
  examples: add Metlino master, Sayma satellite with TTLOuts via FMC
  sayma_amc: add support for 4x DIO output channels via FMC
  fmcdio_vhdci_eem: fix pin naming
  build_soc: add identifier_str override option
  RPC: optimization by caching
  test: improved test_performance
  ...
2020-09-22 16:02:25 +00:00
c55f2222dc fastino: documentation and eem pass-through
* Repeat information about matching log2_width a few times
  in the hope that people read it. #1518
* Pass through log2_width in kasli_generic json. close #1481
* Check DAC value range. #1518
2020-09-22 17:58:53 +02:00
85d16e3e5f phaser: tweaks 2020-09-22 15:27:38 +00:00
fd5e221898 phaser: dac and trf register maps, init code 2020-09-22 14:08:39 +00:00
3e036e365a phaser: nco, settings and init tweaks 2020-09-22 09:52:49 +00:00
fdb2867757 phaser: fewer iotest patterns 2020-09-21 17:06:26 +02:00
d730851397 phaser: elaborate init sequence, more tests 2020-09-21 15:05:29 +00:00
f0959fb871 phaser: iotest early, check_alarms 2020-09-17 14:13:58 +00:00
b15e388b5f ad53xx: distinguish errors 2020-09-17 14:13:10 +00:00
c18f515bf9 phaser: rework rtio channels, sync_dly, init() 2020-09-16 12:23:07 +00:00
f3b0398720 phaser: n=2, m=16, sync_dly 2020-09-16 09:19:15 +00:00
9b58b712a6 phaser: doc tweaks 2020-09-15 12:35:26 +00:00
ff57813a9c phaser: init [wip] 2020-09-15 08:46:47 +00:00
07418258ae phaser: init [wip] 2020-09-15 08:46:10 +00:00
3a79ef740b phaser: work around integer size 2020-09-15 08:46:10 +00:00
b449e7202b phaser: rework docs 2020-09-15 08:46:10 +00:00
b619f657b9 phaser: doc tweaks 2020-09-12 19:59:49 +02:00
c3728678d6 phaser: document, elaborate comments, some fixes 2020-09-12 17:35:14 +00:00
e505dfed5b phaser: refactor coredevice driver 2020-09-12 14:17:40 +00:00
fdd2d6f2fb phaser: SI methods 2020-09-12 11:02:37 +00:00
e69bb0aeb3 phaser: add comment about get_dac_data 2020-09-07 16:06:16 +00:00
6195b1d3a0 rpc: fixed _write_bool
Closes #1519
2020-09-04 13:49:22 +08:00
56aa22caeb fastino: document/cleanup
* added documentation on `update`/`hold` mechanism
* mask machine unit values
* cleanup coredevice driver

close #1518
2020-09-03 17:44:26 +02:00
272dc5d36a phaser: documentation 2020-08-28 16:36:44 +00:00
b2572003ac RPC: optimization by caching
This reduced the calls needed for socket send/recv.
2020-08-28 14:58:34 +08:00
7cf974a6a7 comm_kernel: fix typo 2020-08-28 12:25:23 +08:00
68bfa04abb phaser: trf readback strobe spi changes 2020-08-27 15:31:42 +00:00
c10ac2c92a phaser: add trf, duc, interfaces, redo body assembly, use more natrual iq ordering (i lsb) 2020-08-27 14:26:09 +00:00
e5e2392240 phaser: wire up multidds 2020-08-26 17:12:41 +00:00
d1be1212ab phaser: coredevice shim, dds [wip] 2020-08-26 15:10:50 +00:00
7181ff66a6 compiler: improved rpc performance for list and array
1. Removed duplicated tags before each elements.
2. Use numpy functions to speedup parsing.
2020-08-26 14:17:06 +08:00
20fcfd95e9 phaser: coredevice shim, readback fix 2020-08-24 15:46:31 +00:00
David Nadlinger
8783ba2072 compiler/firmware: RPCs for ndarrays 2020-08-09 17:08:43 +01:00
David Nadlinger
9af6e5747d compiler: Factor rpc_tag() out of llvm_ir_generator 2020-08-09 03:54:41 +01:00
pmldrmota
1df62862cd
AD9910: Write correct number of bits to POW register (#1498)
* coredevice.ad9910: Add return type hints to conversion functions

* coredevice.ad9910: Make set_pow write correct number of bits
The AD9910 expects 16 bits. Thus, if writing 32 bits to the POW register, the chip would likely enter a locked-up state.

* coredevice.ad9910: Correct data alignment in write_16

Co-authored-by: Robert Jördens <rj@quartiq.de>

* coredevice.ad9910: Add function to read from 16 bit registers

Co-authored-by: drmota <peter.drmota@physics.ox.ac.uk>
Co-authored-by: Robert Jördens <rj@quartiq.de>
2020-08-07 10:10:44 +02:00
2a2f5c4d58 comm_analyzer: make header error flag more general 2020-07-20 19:39:19 +08:00
charlesbaynham
2429a266f6
ad9912: Fix typing problem on ad9912 (#1466)
Closes #1463

FTW and phase word were ambiguously typed, resulting in failure to compile
2020-06-16 20:17:22 +02:00
9822b88d9b
ad9910: fix asf range (#1450)
* ad9910: fix asf range

The ASF is a 14-bit word. The highest possible value is 0x3fff, not
0x3ffe. `int(round(1.0 * 0x3fff)) == 0x3fff`.

I don't remember and understand why this was 0x3ffe since the beginning.
0x3fff was already used as a default in `set_mu()`

Signed-off-by: Robert Jördens <rj@quartiq.de>

* RELEASE_NOTES: ad9910 asf scale change

Co-authored-by: David Nadlinger <code@klickverbot.at>
2020-05-29 11:13:26 +02:00
2538840756
Coredevice Input Validation (#1447)
* Input validation and masking of SI -> mu conversions (close #1446)

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* Update RELEASE_NOTES

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

Co-authored-by: Robert Jördens <rj@quartiq.de>
2020-05-17 15:09:11 +02:00
b3b6cb8efe
ad53xx improvements (#1445)
* ad53xx: voltage_to_mu() validation & documentation (closes #1443, #1444)
The voltage input (float) is checked for validity. If we need more
speed, we may want to check the DAC-code for over/underflow instead.

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* ad53xx documentation: voltage_to_mu is only valid for 16-bit DACs

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* AD53xx: add voltage_to_mu method (closes #1341)

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* ad53xx: improve voltage_to_mu performance
Interger comparison is faster than floating point math.

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* AD53xx: voltage_to_mu method now uses attribute values

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* Fixup RELEASE_NOTES.rst

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* ad53xx: documentation improvements

voltage_to_mu return value
14-bit DAC support

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
2020-05-08 19:23:43 +02:00