1
0
forked from M-Labs/artiq
Commit Graph

6 Commits

Author SHA1 Message Date
7f0b2ff594 jesd204sync: work around HMC7043 poor behavior with combined delays
The HMC7043 outputs poorly controlled signals when adjusting
two delays at once. This commit puts the DAC in one-shot SYSREF mode,
and only triggers synchronizations when SYSREF is stable.
2018-08-06 17:43:17 +08:00
f32f0126e2 Revert "ad9154: use continuous sync mode"
The HMC7043 is not really glitchless.

This reverts commit bd968211de.
2018-08-06 16:59:53 +08:00
bd968211de ad9154: use continuous sync mode 2018-08-06 00:27:10 +08:00
446f791180 firmware: simplify SYSREF DRTIO alignment 2018-07-26 19:37:59 +08:00
32c95ac034 sayma: automated DAC SYSREF phase calibration 2018-07-26 16:23:55 +08:00
d523d03f71 sayma: automated FPGA SYSREF phase offset calibration 2018-07-26 14:53:28 +08:00