7d6a1b528d
ad9912: add ftw_to_frequency
2018-08-02 11:19:12 +00:00
e518a1f1d0
ad53xx: also increase slack after control readback
2018-08-02 11:19:12 +00:00
whitequark
5871d13da8
firmware: actually compact in config::compact().
...
Fixes #1116 .
2018-08-01 16:27:48 +00:00
David Nadlinger
829fca6112
pyon: Correctly deserialize bare NaNs
...
This also fixes (non-numpy) lists containing NaNs.
Previously, accidentally storing a NaN in a dataset would
bring down large parts of the system.
2018-07-30 11:08:56 +01:00
David Nadlinger
08ee91beb2
ad9910: Clarify chip_select range [nfc]
...
`assert 3 <= chip_select <= 7` is rather opaque without looking
at the CPLD source code otherwise.
2018-07-30 11:08:17 +01:00
David Nadlinger
6b89106578
ad53xx: Avoid sporadic RTIOUnderflow in init()
...
I observed sporadic RTIO underflows on Kasli before, by ~2.5 µs,
so 5 µs extra slack should be plenty. No underflows since.
2018-07-28 23:45:48 +01:00
e4d48a78eb
drtio: wait for remote to ack TSC synchronization
...
Sayma takes a long time after TSC sync to align SYSREF, and this caused two issues:
1. Aux packets getting lost and causing error reports
2. DRTIO links reported up and kernels proceeding despite the DACs not being properly synced.
2018-07-26 20:28:17 +08:00
83de8b2ba2
drtio: add ping timeout during link init
2018-07-26 20:27:53 +08:00
446f791180
firmware: simplify SYSREF DRTIO alignment
2018-07-26 19:37:59 +08:00
f8c17528e7
satman: use new SYSREF code
2018-07-26 16:26:57 +08:00
32c95ac034
sayma: automated DAC SYSREF phase calibration
2018-07-26 16:23:55 +08:00
dbcf2fe9b4
firmware: remove 'chip found' messages on Sayma
2018-07-26 16:07:37 +08:00
d523d03f71
sayma: automated FPGA SYSREF phase offset calibration
2018-07-26 14:53:28 +08:00
0a9d3638ee
config: add write_int
2018-07-26 14:49:32 +08:00
19c51c644e
grabber: cleanup GRABBER_STATE
2018-07-24 19:08:51 +08:00
fb96c1140e
grabber: add coredevice driver
2018-07-24 18:06:44 +08:00
b38c685857
grabber: fix pix.stb
2018-07-24 11:32:32 +08:00
60a7e0e40d
grabber: use usual order of ROI coordinates in cfg addresses
2018-07-24 10:55:13 +08:00
7b75026391
grabber: add MultiReg to transfer ROI boundaries
2018-07-21 13:40:12 +08:00
4a4d0f8e51
grabber: fix missing variable rename
2018-07-21 13:39:46 +08:00
3638a966e1
kasli: add false path between RTIO and CL clocks
2018-07-21 13:26:13 +08:00
031de58d21
grabber: complete RTIO PHY, untested
2018-07-21 13:25:47 +08:00
e3ba4b9516
grabber: minor ROI engine cleanup, export count_len, cap count width to 31
2018-07-21 13:25:13 +08:00
cab0ba408d
fmcdio_vhdci_eem: cleanup and document
2018-07-20 09:57:03 +08:00
d152506ecb
sayma: update fmcdio_vhdci_eem demo
2018-07-19 15:47:20 +08:00
8dfcd463aa
fmcdio_vhdci_eem: naming consistency
2018-07-19 15:46:04 +08:00
fe93a454d6
fmcdio_vhdci_eem: fix direction shift register permutation and polarity
2018-07-19 15:16:21 +08:00
e71cbe53a6
firmware: cleanup Cargo.lock
2018-07-18 10:37:43 +08:00
31f4f8792a
sayma: add Urukul and Zotino to example device_db
2018-07-18 10:31:55 +08:00
25170a53e5
sayma: add back Urukul and Zotino
2018-07-18 10:27:54 +08:00
5e62910a8d
examples: add Sayma VHDCI DIO
2018-07-17 23:28:05 +08:00
8b9a8be12a
fmcdio_vhdci_eem: add dirctl word computation functions
2018-07-17 23:27:29 +08:00
82145b1263
examples: sayma_drtio → sayma_masterdac
2018-07-17 20:32:30 +08:00
7fe76426fe
fmcdio_vhdci_eem: commit missing part of previous commit
2018-07-17 20:30:13 +08:00
d4d12e264d
fmcdio_vhdci_eem: refactor
...
This allows access to the pin allocation from kernels, which becomes useful
to configure the direction shift register.
2018-07-17 20:13:59 +08:00
4fdc20bb11
sayma: disable Urukul and Zotino for now
...
Ultrascale I/Os are being a pain as usual and the SPI core won't compile.
2018-07-17 20:08:21 +08:00
8335085fd6
fmcdio_vhdci_eem: fix cc pins
2018-07-17 19:50:34 +08:00
8f7c0c1646
fmcdio_vhdci_eem: fix iostandard
2018-07-17 19:40:34 +08:00
d724bd980c
sayma: add EEMs to Master
2018-07-17 18:58:23 +08:00
a0f2d8c2ea
gateware: add FMCDIO/EEM adapter definitions
2018-07-17 18:58:16 +08:00
3645a6424e
sayma: fix Master build
2018-07-17 18:56:33 +08:00
9b016dcd6d
eem: support specifying I/O standard
...
Xilinx FPGAs require different LVDS I/O standard names depending on I/O bank voltage.
2018-07-17 18:55:17 +08:00
3168b193e6
kc705: remove Zotino and Urukul
...
* use Kasli instead for using EEMs
* code required outdated VHDCI adapter 1.0
2018-07-17 17:48:57 +08:00
13984385a8
firmware: version → ident
2018-07-15 17:40:17 +08:00
b2695d03ed
sayma: remove with_sawg from Master variant
2018-07-15 17:38:29 +08:00
123e7bc054
pyon: sort string dicts by key when pretty-printing. Closes #1010
2018-07-15 17:38:09 +08:00
b27fa8964b
add variant in identifier string
...
Also add without-sawg suffixes on Sayma.
Closes #1060
Closes #1059
2018-07-15 17:21:17 +08:00
b6c70b3cb0
eem: add Zotino monitoring. Closes #1095
2018-07-15 15:35:04 +08:00
8bcba82b65
grabber: reset *_good signals on end of frame
...
This reduces the amount of time the ROI engine produces invalid output after
being reconfigured.
2018-07-15 15:34:00 +08:00
ea7f925852
Revert "worker_db: Only warn on repeated archive read if dataset changed"
...
Breaks numpy arrays.
This reverts commit 141fcaaa8a
2018-07-13 10:41:06 +08:00
46fb5adac3
grabber: fix frequency counter formula
2018-07-12 20:14:38 +08:00
82def6b535
grabber: add frequency counter
...
Cameras are a bit obscure about what they output, this can help with troubleshooting.
2018-07-12 17:05:18 +08:00
29c35ee553
hmc7043: fix dumb mistake in previous commit
2018-07-12 13:01:41 +08:00
8802b930de
hmc7043: add delay after init
...
Delay required at step 9 of the "Typical Programming Sequence" (page 24 of the datasheet)
2018-07-12 12:37:12 +08:00
c66f9483f8
hmc7043: wait after changing delays
...
Allows for the SPI transaction to finish, and for the delay to stabilize.
2018-07-12 12:33:53 +08:00
1c191a62bf
sayma: tune SYSREF phases
2018-07-12 12:33:35 +08:00
773240bef4
hmc7043: test GPO before using
...
Based on code by David.
2018-07-12 11:30:24 +08:00
David Nadligner
141fcaaa8a
worker_db: Only warn on repeated archive read if dataset changed
...
In larger experiments, it is quite natural for the same dataset
to be read from multiple unrelated components. The only situation
where multiple reads from an archived dataset are problematic is
when the valeu actually changes between reads. Hence, this commit
restricts the warning to the latter situation.
2018-07-12 10:15:42 +08:00
4843832329
hmc7043: check phase status on init. Closes #1055
...
Troubleshooting by David.
2018-07-11 19:45:24 +08:00
9397fa7f5a
hmc7043: unstick SYSREF FSM ( #1055 )
...
Troubleshooting by David.
Additionally, register 7D is broken.
Checking phase init state has to be done through another means.
2018-07-11 19:11:01 +08:00
88fb9ce4d6
sayma_rtm: add hmc7043_gpo monitoring
2018-07-11 19:04:29 +08:00
29e5c95afa
sayma_rtm: minor cleanup
2018-07-11 19:02:59 +08:00
7f05e0c121
sayma_rtm: remove UART loopback
...
RTM power supply issues are fixed now, plus this will get in the way of satman support.
2018-07-11 19:00:18 +08:00
f8ceea20d0
grabber: add new ROI engine (untested)
2018-07-10 17:06:17 +08:00
d82beee540
grabber: make parser EOP a pulse
2018-07-10 17:04:07 +08:00
701c93d46c
grabber: add false path constraints
2018-07-10 14:28:23 +08:00
6a77032fa5
grabber: use BUFR/BUFIO
...
Less jitter and frees up BUFGs.
2018-07-10 13:30:38 +08:00
208dc7c218
grabber: prevent glitches in last_x/last_y cdc
2018-07-10 12:56:37 +08:00
c4e3c66265
grabber: add clock constraint
2018-07-10 12:37:32 +08:00
David Nadlinger
768b970deb
Fixup 4359a437 (tuples of lists), add regression tests
2018-07-10 01:18:51 +01:00
David Nadlinger
edc314524c
test_embedding: Remove unused reference to led device
2018-07-10 01:11:47 +01:00
4f56710e4b
grabber: add parser, report detected frame size in core device log
2018-07-10 02:06:37 +08:00
David Nadlinger
4359a43732
compiler: Indirection status of TTuple depends on elements
...
For instance, TTuple(TList(TInt32())) has indirections, while
TTuple(TInt32()) does not.
This fixes memory corruption with RPCs that return tuples of lists.
Signed-off-by: David Nadlinger <code@klickverbot.at>
2018-07-09 18:49:50 +08:00
d2c8e62cb7
test_rtio: relax ClockGeneratorLoopback performance requirements
2018-07-09 18:07:25 +08:00
423929a125
test: relax min transfer rates from 2MB/s to 1.9MB/s
2018-07-09 18:00:24 +08:00
9153c4d8a3
use tokenize.open() to open Python source files
...
Fixes encoding issues especially with device databases modified in obscure editors.
2018-07-07 17:04:56 +08:00
4420046502
kasli_tester: support mixed AD9910/AD9912 systems
2018-07-06 15:43:38 +08:00
ac3f360c26
kasli_tester: fix AD9912 support
2018-07-06 15:43:25 +08:00
509562ddbf
kasli: add WIPM target
2018-07-06 15:41:28 +08:00
4eb26c0050
hmc7043: enable group 5
2018-07-03 14:16:31 +02:00
540bdae99c
grabber: enable DIFF_TERM on inputs
2018-07-01 09:28:51 +08:00
0483b8d14c
sayma_drtio: ditto
2018-06-28 17:03:32 +08:00
04d6ff45c8
kasli_sawgmaster: reset SAWGs
...
Most importantly this resets the phase accumulators.
2018-06-28 17:01:48 +08:00
729ce58f98
sayma: use GTP_CLK1 to clock DRTIO satellite transceiver
...
This is required to get constant skew between the DRTIO transceiver clock
(which then generates the RTIO clock) and the siphaser reference clock.
Both the Si5324 and the RTM clock tree have non-deterministic in-to-out skew
at 150MHz due to dividers.
2018-06-28 11:23:40 +08:00
a65721d649
sayma: put RTM clock tree into the siphaser loop
...
* Fixes one bug where siphaser was one Si5324 output and the rest of the
system was clocked by the other. With the Si5324 settings we have, skew
between the outputs is not controlled.
* Puts the coaxial cable between AMC and RTM into the siphaser loop.
2018-06-27 21:46:55 +08:00
d49716dfac
satman: tune Sayma SYSREF phases
2018-06-27 18:09:35 +08:00
46c044099c
hmc7043,satman: verify alignment of SYSREF slips
2018-06-27 17:36:13 +08:00
7dfd70c502
hmc7043: make margin_{minus,plus} consistent with ad9154
2018-06-27 17:35:26 +08:00
4bbdd43bdf
hmc7043: do not freeze if SYSREF slip fails
2018-06-27 17:32:56 +08:00
a8a2ad68d3
runtime: tune Sayma SYSREF phases
2018-06-27 17:31:29 +08:00
811882943b
artiq_flash: RTM gateware is not required for master variant
2018-06-25 18:28:55 +08:00
c750de2955
sayma: add many-port pure DRTIO master
2018-06-25 18:21:22 +08:00
84b3d9ecc6
bootloader: also check firmware CRC in SDRAM ( #1065 )
2018-06-23 11:28:12 +08:00
68530fde07
sayma: generate 100MHz from Si5324 on standalone and master targets
...
* Allow switching between DRTIO satellite and standalone without
touching the hardware.
* Allow operating standalone and master without an additional RF
signal generator.
2018-06-23 10:44:38 +08:00
whitequark
b6dd9c8bb0
runtime: support builds without RTIO DMA.
...
Fixes #1079 .
2018-06-23 00:56:21 +00:00
whitequark
12fde6d34b
artiq_coremgmt: fix typo.
...
Fixes #1056 .
2018-06-23 00:36:59 +00:00
51a5d8dff9
examples: add Kasli SAWG master
2018-06-22 18:57:49 +08:00
f87da95e57
jesd204: use jesd clock domain for sysref sampler
...
RTIO domain is still in reset during calibration.
2018-06-22 17:13:01 +08:00
76fc63bbf7
jesd204: use separate controls for reset and input buffer disable
2018-06-22 11:38:18 +08:00
d9955fee76
jesd204: make sure IOB FF is used to sample SYSREF at FPGA
2018-06-22 11:00:56 +08:00
60b22217ce
sayma: set DRTIO master HMC830_REF to 100MHz
2018-06-22 10:10:09 +08:00
e6d1726754
sayma: add RTIO log to DRTIO master
2018-06-22 00:05:22 +08:00
83428961ad
sayma: add SAWG and JESD to DRTIO master
2018-06-22 00:04:22 +08:00
c1db02a351
drtio/gth_ultrascale: disable IBUFDS_GTE3 until stable_clkin
...
Precaution against HMC7043 noise issues.
2018-06-21 22:56:07 +08:00
8b3c12e6eb
sayma: clock DRTIO master transceiver from HMC7043
2018-06-21 22:34:44 +08:00
de7d64d482
sayma: clock JESD204 from GTP CLK2
...
This frees up GTP CLK1, which is routable to the SFP quads, for DRTIO.
2018-06-21 22:33:53 +08:00
b28ff587c5
sayma: add sysref sampler to DRTIO master
2018-06-21 22:28:34 +08:00
07bcdfd91e
hmc7043: stricter check of FPGA SYSREF margin
2018-06-21 22:26:49 +08:00
e29536351d
drtio: resync SYSREF when TSC is loaded
2018-06-21 17:00:32 +08:00
5a2a857a2f
firmware: clean up SYSREF phase management
2018-06-21 16:23:41 +08:00
05e908a0fd
hmc7043: align SYSREF with RTIO
2018-06-21 15:54:42 +08:00
9741654cad
hmc7043: style
2018-06-21 15:54:42 +08:00
45e8263208
hmc7043: do not configure phases during initial init
...
They are determined later on.
2018-06-21 15:54:42 +08:00
whitequark
7cc3da4faf
firmware: do not lose the ".dirty" suffix in build versions.
...
Fixes #1074 .
2018-06-21 05:18:51 +00:00
whitequark
095ee28fd9
runtime: fix size values for bytes and bytearray RPCs.
...
Fixes #1076 .
2018-06-21 00:51:56 +00:00
whitequark
9260cdb2e8
compiler: support conversion of list to bytearray and bytes.
...
Fixes #1077 .
2018-06-21 00:40:45 +00:00
5a91f820fd
examples: change Sayma sines frequency to 9MHz
...
Well within Red Pitaya bandwidth.
2018-06-20 22:40:07 +08:00
9288301543
examples: add DRTIO sines
2018-06-20 22:39:40 +08:00
28fb0fd754
sayma: add SYSREF sampler gateware
2018-06-20 17:48:35 +08:00
814d0583db
hmc7043: improve smoothness of sysref phase control
2018-06-20 17:40:48 +08:00
9142a5ab8a
rtio: expose coarse timestamp in RTIO and DRTIO satellite cores
2018-06-20 17:39:54 +08:00
5272c11704
typo
2018-06-20 17:05:20 +08:00
0c32d07e8b
ad9154: new sysref scan
...
Print margins around the pre-defined fixed phase.
Also report error if margins are too small.
The fixed phase is also changed by this commit (the value 88 is
from before the new HMC7043 initialization code, and is probably wrong).
2018-06-20 00:15:58 +08:00
4803ca3799
examples/sayma_drtio: add SAWG channels
2018-06-19 23:50:26 +08:00
3d0e92aefd
hmc7043: check that chip is disabled at startup
2018-06-19 23:49:17 +08:00
740e6863c3
hmc7043: add delay after releasing hardware reset
2018-06-19 23:48:48 +08:00
75b6cea52f
sayma: add SAWG to DRTIO satellite
2018-06-19 19:12:10 +08:00
eb3259b847
firmware: reduce number of DAC initialization attempts
...
Faster startup when one DAC is broken.
2018-06-19 19:10:23 +08:00
1d594d0c97
firmware: make DAC initialization failures non-fatal
...
This allows using RTMs with one broken DAC for development.
2018-06-19 19:09:38 +08:00
158b5e3083
satman: program Allaki
2018-06-19 18:09:05 +08:00
574892a4e5
firmware/serwb: cleanup and improve messaging
2018-06-19 15:11:03 +08:00
c862471165
typo
2018-06-19 14:35:24 +08:00
433273dd95
sayma: support RTM FPGA, HMC830 and HMC7043 in DRTIO master and satellite
2018-06-19 14:33:48 +08:00
476cfa0f53
si5324: improve lock messaging
2018-06-19 14:29:57 +08:00
6403a0d5d1
sayma_amc: update without-sawg description
2018-06-19 13:52:05 +08:00
d29b3dd588
hmc830: compile-time configurable reference frequency
2018-06-19 13:47:32 +08:00
6f3ed81626
targets/sayma_rtm: fix description
2018-06-18 17:46:53 +08:00
21a48711ec
i2c: refactor common operations
2018-06-18 09:34:09 +00:00
0e640a6d6f
hmc7043: fix SYSREF to meet s/h at FPGA ( #794 )
2018-06-18 17:04:12 +08:00
6272052d15
ad9154: don't drive the bsm with txen pins
2018-06-18 10:04:42 +02:00
32484a62de
sayma_amc: remove unused imports
2018-06-17 13:09:44 +02:00
4f0c918dd3
slave_fpga: improve messaging
2018-06-17 00:27:27 +08:00
53ab255c00
sayma_amc: enable slave fpga loading ( #813 )
2018-06-16 12:47:26 +02:00
f9910ab242
i2c: support selecting multiple or no channels
...
closes #1054
2018-06-15 19:36:37 +02:00
40baa8ecba
hmc7043: disable ch 10 and 11 group
2018-06-15 15:34:31 +00:00
edfae3c4ba
hmc7043: make fpga fabric clocks lvds
...
2 V common and 1.9 Vpp swing
is brutal to the banks (HP 1.8V AMC and RT 1.8V RTM)
2018-06-15 14:24:33 +00:00
f385add8b1
slave_fpga: disable cclk and din drive when done
...
to guard against accidental contention (old rtm gateware
but #813 rework done)
2018-06-13 16:26:48 +00:00
1029ac870b
sayma_rtm: don't drive txen pins
...
pins disabled by config
necessary for using that pin as DIN (#813 )
2018-06-13 16:11:30 +00:00
68d16fc292
serwb: support single-ended signals
...
Low-speed PHY only.
2018-06-13 21:28:21 +08:00
a9a25f2605
sayma_rtm: drive ref_lo_clk_sel, and set clk muxes early
2018-06-12 20:00:12 +02:00
