Florent Kermarrec
825a2158ba
serwb: add phy_width parameter to allow reducing linerate to 500Mbps or 250Mbps
2018-04-16 23:19:14 +02:00
Florent Kermarrec
bb90fb7d59
sayma/serwb: remove scrambling (does not seems to work on sayma for now...)
2018-04-07 15:57:57 +02:00
Florent Kermarrec
6aa8e2c433
serwb/test: replace valid/ready with stb/ack
2018-04-07 15:55:57 +02:00
Florent Kermarrec
73dbc0b6b6
serwb/test: adapt to new version
2018-04-07 15:09:29 +02:00
Florent Kermarrec
e15f8aa903
sayma/serwb: enable scrambling
2018-04-07 14:52:37 +02:00
Florent Kermarrec
9d0e8c27ff
serwb/scrambler: add flow control
2018-04-07 14:51:17 +02:00
Florent Kermarrec
2f8bd022f7
sayma_rtm: remove sys0p2x clock
2018-04-07 03:10:34 +02:00
Florent Kermarrec
1fd96eb0fd
serwb: replace valid/ready with stb/ack
2018-04-07 03:06:19 +02:00
Florent Kermarrec
c8a08375f8
serwb: replace valid/ready with stb/ack
2018-04-07 03:03:44 +02:00
Florent Kermarrec
73b727cade
serwb: new version using only sys/sys4x clocks domains, scrambling deactivated.
2018-04-07 02:59:14 +02:00
Florent Kermarrec
dd21c07b85
targets/sayma_rtm: fix serwb 2 ...
2018-04-03 18:59:05 +02:00
Florent Kermarrec
7488703f23
targets/sayma_rtm: fix serwb
2018-04-03 18:57:00 +02:00
Florent Kermarrec
aef0153a8f
targets/sayma: adapt to new serwb clocking
2018-04-03 18:53:39 +02:00
Florent Kermarrec
3248caa184
gateware/serwb: move all clocking outside of serwb, use existing sys/sys4x clocks
2018-04-03 18:48:08 +02:00
f0771765c1
rtio: move CRI write comment to more appropriate location
2018-03-29 23:55:00 +08:00
493d2a653f
siphaser: add false path between sys_clk and mmcm_freerun_output
2018-03-29 10:55:41 +08:00
4229c045f4
kasli: fix DRTIO master clock constraint
2018-03-29 10:20:31 +08:00
3d89ba2e11
sayma: remove debug leftover
2018-03-29 10:20:17 +08:00
605292535c
kasli: ignore OSERDESE2->ISERDESE2 timing path on DRTIO targets as well
2018-03-29 10:12:02 +08:00
416232cb64
runtime: do not reset RTIO PHY on core.reset(). Closes #971
2018-03-28 10:51:07 +08:00
5ca59467fd
ad53xx: make LDAC and CLR optional
2018-03-26 22:45:01 +08:00
whitequark
bab6723ff2
Revert "gateware: don't run tests if there is no migen."
...
This reverts commit 4804cfef9b
2018-03-26 03:33:52 +00:00
whitequark
4804cfef9b
gateware: don't run tests if there is no migen.
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This allows us to skip testing gateware on Windows.
2018-03-26 03:26:34 +00:00
whitequark
87c2f119a5
artiq_devtool: add load action.
2018-03-25 20:29:51 +00:00
8d62ea2288
examples: fix KC705 ad53xx
2018-03-25 11:19:54 +08:00
c3f763e217
dashboard: also create monitoring widgets for the Zotino class
2018-03-25 11:19:40 +08:00
a20dfd9c00
examples/master: ad5360 -> zotino
2018-03-24 16:46:59 +01:00
0505e9124f
kc705: port device_db, ad53xx/zotino example
2018-03-24 16:05:26 +01:00
3a0dfb7fdc
ad53xx: port monitor, moninj dashboard, kc705 target
2018-03-24 16:04:02 +01:00
a8f0ee1c86
ad53xx: refactor offset_to_mu(), fix docs
2018-03-24 15:45:42 +01:00
b0c8097025
ad53xx: remove channel index AND
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It's incorrect since it doesn't respect the number of channels
of any of those chips (none has 64 channels).
2018-03-24 15:39:06 +01:00
77bcc2c78f
zotino: style, use attributes to set SPI config
2018-03-24 15:37:34 +01:00
2cf414a480
ad53xx: move 8 bit shift out of ad53xx protocol funcs
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That's specific to the SPI bus, not to the ad53xx.
2018-03-24 15:15:56 +01:00
08326c5727
ad53xx: style [nfc]
2018-03-24 14:10:20 +01:00
68e433a3a8
opticlock/device_db: resurrect novogorny
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deleted in a992a67
2018-03-24 13:46:45 +01:00
hartytp
a992a672d9
coredevice/zotino: add ( #969 )
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* Replace ad5360 driver with a ad53xx driver, designed to have a nicer interface
Add Zotino driver and add to opticlock target for Kasli
Test Zotino on hw:
- Verify all timings on the hardware with a scope
- Verify that we can correctly set and read back all registers in a loop (checks for SI and driver issues)
- check we can set LEDs correctly
- check calibration routine + all si unit functions with a good DVM
- look at DAC transitions on a scope (while triggering of a TTL) on persist to check there are no LDAC glitches etc
To do: update examples and e.g. KC705 device db.
2018-03-24 13:41:18 +01:00
1553fc8c7d
sed: reset valid in output sorter
2018-03-23 11:11:11 +00:00
0635907699
artiq_flash: fix cmdline formatting
2018-03-22 19:10:29 +08:00
46d5af31a1
artiq_flash: enclose filename in curly braces before passing to OpenOCD
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Closes #927
2018-03-22 17:20:48 +08:00
eeedcfbdd7
artiq_flash: do not suppress useful backtrace information
2018-03-22 17:11:21 +08:00
f2cc2a5ff2
firmware: reset local RTIO PHYs on startup ( #958 )
2018-03-22 16:29:31 +08:00
770b0a7b79
novogorny: conv -> cnv
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* parity with sampler
* also add novogorny device to opticlock
2018-03-21 18:38:42 +00:00
82c4f0eed4
sampler: fix channel gain retrieval
2018-03-21 14:22:13 +01:00
12d699f2a8
suservo: add sampler example
2018-03-21 12:21:53 +00:00
97918447a3
sampler: add coredevice driver
2018-03-21 12:21:53 +00:00
1afce8c613
kasli: simplify single eem pin formatting
2018-03-21 13:08:42 +01:00
d48b8f3086
kasli: fix sampler sdr/cnv pins
2018-03-21 09:28:00 +00:00
80903cead7
novogorny: streamline gain setting method, style [nfc]
2018-03-21 08:53:26 +00:00
f5a1001114
suservo: add device database and artiq_flash variant
2018-03-21 08:53:26 +00:00
1fb5907362
kasli: add SUServo variant (Sampler-Urukul Servo)
2018-03-21 08:53:26 +00:00
f74d5772f4
sampler: add wide eem definition
2018-03-21 08:53:26 +00:00
32f22f4c9c
sayma: disable SERDES TTL entirely
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Timing closure becomes very random, even at 4X.
2018-03-21 13:03:48 +08:00
f8c2d54e75
ttl_serdes_ultrascale: configurable SERDES ratio. Also try X4 on Sayma
2018-03-21 13:01:38 +08:00
9c2d343052
sayma: use SERDES RTIO TTL
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This is not enabled on the standalone design as it breaks timing.
2018-03-21 10:53:52 +08:00
9ad1fd8f25
urukul: add comment and doc about the AD9910 MASTER_RESET
2018-03-20 17:40:03 +01:00
f17c0abfe4
urukul: don't pulse DDS_RST on init
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closes m-labs/artiq#940
Apparently, if the DDS are reset, every other time they don't work
properly.
2018-03-20 16:10:26 +00:00
a185e8dc52
urukul: fix MASK_NU offset
2018-03-20 16:10:11 +00:00
f4719ae24b
sdram: clean up console output
2018-03-20 15:42:49 +01:00
206664afd9
sdram: compact read_level output
2018-03-20 10:16:05 +00:00
495625b99d
bootloader: repeat memory test 4 times
2018-03-20 09:57:49 +00:00
6fb0cbfcd3
sdram: clean up, make read_level robust to wrap around
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* fix a few rust warnings
* also do eye scans on kintex
2018-03-20 09:57:49 +00:00
3abb378fbe
i2c: unused variable
2018-03-20 09:56:26 +00:00
c8020f6bbd
ttl_serdes_generic: fix/upgrade test
2018-03-20 16:46:57 +08:00
a5825184b7
add ttl_serdes_ultrascale (untested)
2018-03-20 16:07:23 +08:00
fad066f1aa
ttl_serdes_7series: cleanup indentation
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Inconsistent with other code and confuses text editors.
2018-03-20 15:50:04 +08:00
276b0c7f06
sdram: reject read delay wrap arounds
2018-03-20 00:28:41 +01:00
4b3f408143
sdram: simplify read level scan
2018-03-19 18:41:56 +00:00
845784c180
kusddrphy: use first and last tap that yield many valid reads
2018-03-19 17:54:26 +00:00
ed2e0c8b34
sayma/sdram/scan: test each tap 1024 times
2018-03-20 00:59:31 +08:00
hartytp
a27b5d88c2
Novogorny driver, remove unused imports ( #964 )
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* Novogorny driver, remove unused imports
* more unused imports
* oops, one final one!
2018-03-19 11:58:14 +01:00
7a7ff6d2dd
Merge pull request #963 from hartytp/kasli_zotino_sampler
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Add Zotino and Sampler functions to Kasli. Add Zotino to Kasli EEM 7 …
2018-03-19 10:52:50 +01:00
Thomas Harty
37d431039d
Fix typos.
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Reduce ififo depth to 4 for Zotino.
2018-03-19 09:42:18 +00:00
whitequark
c86df8e13e
firmware: try to unstuck the I2C bus if it gets stuck.
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Fixes #957 .
2018-03-19 06:23:23 +00:00
Thomas Harty
c4fa44bc62
Add Zotino and Sampler functions to Kasli. Add Zotino to Kasli EEM 7 on OptiClock.
2018-03-18 00:25:43 +00:00
f39b7b33e8
ad5360: whitespace [nfc]
2018-03-17 18:51:17 +01:00
ion
c1439bfd3b
Fix AD5360 after migration to SPI2
2018-03-17 11:37:11 +00:00
whitequark
4b5a78e231
compiler: do not pass files to external tools while they are opened.
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This fixes access violations on Windows that are present both with
input and output files. For some reason, Cygwin-compiled binutils
did not exhibit this problem, but MSYS-compiled binutils do.
Fixes #961 .
2018-03-15 22:21:29 +00:00
whitequark
5cb2602021
artiq_devtool: flash gateware if -g is passed.
2018-03-15 08:33:53 +00:00
whitequark
9ea7d7a804
firmware: allow building without system UART.
2018-03-14 18:34:31 +00:00
whitequark
158ceb0881
artiq_devtool: add kasli target.
2018-03-14 18:13:13 +00:00
a315ecd10b
rtio/ttl_serdes_7series: reset IOSERDES ( #958 )
2018-03-14 09:01:29 +08:00
2fdc180601
dsp/fir: outputs reset_less (pipelined)
2018-03-13 17:11:50 +00:00
2edf65f57b
drtio: fix satellite minimum_coarse_timestamp clock domain ( #947 )
2018-03-13 00:20:57 +08:00
999ec40e79
bootloader: print gateware ident
2018-03-13 00:11:25 +08:00
2caeea6f25
update copyright year
2018-03-13 00:09:13 +08:00
1d081ed6c2
drtio: print diagnostic info on satellite write underflow ( #947 )
2018-03-12 23:41:19 +08:00
Florent Kermarrec
eb6e59b44c
sayma_rtm: fix serwb timing constraints (was causing the gated clock warning)
2018-03-12 11:25:29 +01:00
6dfebd54dd
ttl_serdes_7series: use correct IBUFDS_INTERMDISABLE port names
2018-03-12 10:37:33 +08:00
a04bd5a4fd
spi2: xfers take one more cycle until ~busy
2018-03-09 20:48:17 +01:00
Florent Kermarrec
5af4609053
libboard/sdram: limit write leveling scan to "512 - initial dqs taps delay" on ultrascale
2018-03-09 19:06:47 +01:00
Florent Kermarrec
a95cd423cc
libboard/sdram: add gap for write leveling
2018-03-09 18:53:57 +01:00
fc3d97f1f7
drtio: remove spurious multichannel transceiver clock constraints
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They used to cause (otherwise harmless) Vivado critical warnings.
2018-03-09 22:46:27 +08:00
caf7b14b55
kasli: generate fine RTIO clock in DRTIO targets, separate RTIO channel code
2018-03-09 22:36:16 +08:00
Florent Kermarrec
8f6f83029c
libboard/sdram: add write/read leveling scan
2018-03-09 13:50:51 +01:00
Florent Kermarrec
b0b13be23b
libboard/sdram: rename read_delays to read_leveling
2018-03-09 09:23:20 +01:00
3fbcf5f303
drtio: remove TSC correction ( #40 )
2018-03-09 10:36:17 +08:00
e38187c760
drtio: increase default underflow margin. Closes #947
2018-03-09 00:49:24 +08:00
37f5f0d38d
examples: add DMA to Sayma DRTIO
2018-03-09 00:49:24 +08:00
Florent Kermarrec
8475c21c46
firmware/libboard/sdram: kusddrphy now use time mode for odelaye3/idelaye3, now reloading dqs delay_value (500ps) with software
2018-03-08 10:00:00 +01:00
8bd15d36c4
drtio: fix error CSR edge detection ( #947 )
2018-03-08 16:28:25 +08:00
