From e50bebb63db94c72bfc7fe8b8b802cc9b820c1e5 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 5 Feb 2018 13:39:30 +0100
Subject: [PATCH] firmware/liboard_artiq/ad9154.rs: add checks for jesd
 subclass 1 (verify that we receive the sysref and that phase error is within
 the specified window error threshold).

---
 artiq/firmware/libboard_artiq/ad9154.rs | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/artiq/firmware/libboard_artiq/ad9154.rs b/artiq/firmware/libboard_artiq/ad9154.rs
index d30cb6adf..c683ccc47 100644
--- a/artiq/firmware/libboard_artiq/ad9154.rs
+++ b/artiq/firmware/libboard_artiq/ad9154.rs
@@ -374,9 +374,15 @@ fn dac_setup(dacno: u8, linerate: u64) -> Result<(), &'static str> {
             1*ad9154_reg::SYNCARM | 0*ad9154_reg::SYNCCLRSTKY |
             0*ad9154_reg::SYNCCLRLAST);
     clock::spin_us(1000); // ensure at least one sysref edge
+    if read(ad9154_reg::SYNC_CONTROL) & ad9154_reg::SYNCARM != 0 {
+        return Err("AD9154 no sysref edge");
+    }
     if read(ad9154_reg::SYNC_STATUS) & ad9154_reg::SYNC_LOCK == 0 {
         return Err("AD9154 no sync lock");
     }
+    if read(ad9154_reg::SYNC_STATUS) & ad9154_reg::SYNC_WLIM != 0 {
+        return Err("AD9154 sysref phase error");
+    }
     write(ad9154_reg::XBAR_LN_0_1,
             0*ad9154_reg::LOGICAL_LANE0_SRC | 1*ad9154_reg::LOGICAL_LANE1_SRC);
     write(ad9154_reg::XBAR_LN_2_3,