From ce73e8eea768c75c0947e98cea0e23d019d69a26 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 14 Jul 2016 15:59:21 +0800 Subject: [PATCH] target/pipistrello: shrink TTL FIFOs --- artiq/gateware/targets/pipistrello.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index 5bd048c6a..feb744a21 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -177,7 +177,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i), self.rtio_crg.rtiox4_stb) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512, + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=64, ofifo_depth=4)) # the last TTL is used for ClockGen @@ -192,7 +192,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd phy = ttl_simple.Output(platform.request("ttl", i)) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256)) + rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=64)) phy = ttl_simple.Output(platform.request("ext_led", 0)) self.submodules += phy