From bb91582accf05c1893d7ba29449652b0626de018 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 13 May 2018 23:39:44 +0800 Subject: [PATCH] coredevice/dds: fix init_duration_mu and init_sync_duration_mu --- artiq/coredevice/dds.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/coredevice/dds.py b/artiq/coredevice/dds.py index 5c7293edf..f64fad876 100644 --- a/artiq/coredevice/dds.py +++ b/artiq/coredevice/dds.py @@ -291,8 +291,8 @@ class DDSGroupAD9914(DDSGroup): self.write_duration_mu = 5 * self.rtio_period_mu self.dac_cal_duration_mu = 147000 * self.rtio_period_mu - self.init_duration_mu = 8 * self.write_duration_mu + self.dac_cal_duration_mu - self.init_sync_duration_mu = 16 * self.write_duration_mu + 2 * self.dac_cal_duration_mu + self.init_duration_mu = 9 * self.write_duration_mu + self.dac_cal_duration_mu + self.init_sync_duration_mu = 17 * self.write_duration_mu + 2 * self.dac_cal_duration_mu self.program_duration_mu = 6 * self.write_duration_mu self.continuous_phase_comp = [0] * (self.dds_bus_count * self.dds_channel_count)