From 93882eb3cefc42fb02d8b91594e56db2a1531a9e Mon Sep 17 00:00:00 2001 From: den512 Date: Tue, 27 Jun 2023 13:10:33 +0800 Subject: [PATCH] kasli-soc: fix of SYS CLK switch failure Change initialization behaviour of GTX transceivers -- Modify the config parms CPLL of GTX transceiver for PLL to lock correctly Modify the enabling requirement of GTX input clock buffer IBUFDS_GTE2 so that it depends on GTX PLL locked signal instead of TX Init Done Modify the GTX Init FSM so that BruteForceClock Aligner can reset GTX transceiver without resetting the GTX transceiver PLL kasli-soc: fix of SYS CLK switch failure Changed initialization of GTX transceivers. Successful SYS CLK switching requires IBUFDS_GTE2 to be properly enabled and not disabled during GTX transceiver initialization. For this reason, CPLL is not reset during GTX initialization and clock alignment. kasli-soc: refractor fix of SYS CLK switch failure Remove gtXxreset & cpllreset assertion and deassertion The removed code does not affect the fix --- artiq/gateware/drtio/transceiver/gtx_7series.py | 4 +++- .../gateware/drtio/transceiver/gtx_7series_init.py | 13 +++++++++---- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/artiq/gateware/drtio/transceiver/gtx_7series.py b/artiq/gateware/drtio/transceiver/gtx_7series.py index a1872e8ae..f62663895 100644 --- a/artiq/gateware/drtio/transceiver/gtx_7series.py +++ b/artiq/gateware/drtio/transceiver/gtx_7series.py @@ -74,6 +74,8 @@ class GTX_20X(Module): p_CPLL_REFCLK_DIV=1, p_RXOUT_DIV=2, p_TXOUT_DIV=2, + p_CPLL_INIT_CFG=0x00001E, + p_CPLL_LOCK_CFG=0x01C0, i_CPLLRESET=cpllreset, i_CPLLPD=cpllreset, o_CPLLLOCK=cplllock, @@ -320,7 +322,7 @@ class GTX(Module, TransceiverInterface): # stable_clkin resets after reboot since it's in SYS domain # still need to keep clk_enable high after this - self.sync.bootstrap += clk_enable.eq(self.stable_clkin.storage | self.gtxs[0].tx_init.done) + self.sync.bootstrap += clk_enable.eq(self.stable_clkin.storage | self.gtxs[0].tx_init.cplllock) # Connect slave i's `rtio_rx` clock to `rtio_rxi` clock for i in range(nchannels): diff --git a/artiq/gateware/drtio/transceiver/gtx_7series_init.py b/artiq/gateware/drtio/transceiver/gtx_7series_init.py index 5552c308f..0e30ee27c 100644 --- a/artiq/gateware/drtio/transceiver/gtx_7series_init.py +++ b/artiq/gateware/drtio/transceiver/gtx_7series_init.py @@ -110,9 +110,9 @@ class GTXInit(Module): startup_fsm.act("INITIAL", startup_timer.wait.eq(1), - If(startup_timer.done & self.stable_clkin, NextState("RESET_ALL")) + If(startup_timer.done & self.stable_clkin, NextState("RESET_PLL")) ) - startup_fsm.act("RESET_ALL", + startup_fsm.act("RESET_PLL", gtXxreset.eq(1), self.cpllreset.eq(1), pll_reset_timer.wait.eq(1), @@ -120,7 +120,12 @@ class GTXInit(Module): ) startup_fsm.act("RELEASE_PLL_RESET", gtXxreset.eq(1), - If(cplllock, NextState("RELEASE_GTH_RESET")) + If(cplllock, NextState("RESET_GTH")) + ) + startup_fsm.act("RESET_GTH", + gtXxreset.eq(1), + pll_reset_timer.wait.eq(1), + If(pll_reset_timer.done, NextState("RELEASE_GTH_RESET")) ) # Release GTX reset and wait for GTX resetdone # (from UG476, GTX is reset on falling edge @@ -229,7 +234,7 @@ class GTXInit(Module): startup_fsm.act("READY", Xxuserrdy.eq(1), self.done.eq(1), - If(self.restart, NextState("RESET_ALL")) + If(self.restart, NextState("RESET_GTH")) )