From 72a6ff6e9c2fc899decea87609e377890976c65e Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sat, 26 Mar 2022 17:23:13 +0800
Subject: [PATCH] urukul: make RF switch TTL optional

---
 artiq/coredevice/ad9910.py                | 7 ++++---
 artiq/coredevice/ad9912.py                | 9 +++++----
 artiq/examples/nac3devices/nac3devices.py | 2 +-
 3 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py
index 23d2856f2..f8d0e1ff4 100644
--- a/artiq/coredevice/ad9910.py
+++ b/artiq/coredevice/ad9910.py
@@ -158,7 +158,7 @@ class AD9910:
     ftw_per_hz: KernelInvariant[float]
     sysclk_per_mu: KernelInvariant[int32]
     sysclk: KernelInvariant[float]
-    sw: KernelInvariant[TTLOut]
+    sw: KernelInvariant[Option[TTLOut]]
     sync_data: KernelInvariant[SyncDataUser]
     phase_mode: Kernel[int32]
 
@@ -175,8 +175,9 @@ class AD9910:
         assert 3 <= chip_select <= 7
         self.chip_select = chip_select
         if sw_device:
-            self.sw = dmgr.get(sw_device)
-            # NAC3TODO: support no sw
+            self.sw = Some(dmgr.get(sw_device))
+        else:
+            self.sw = none
         clk = self.cpld.refclk / [4, 1, 2, 4][self.cpld.clk_div]
         self.pll_en = pll_en
         self.pll_n = pll_n
diff --git a/artiq/coredevice/ad9912.py b/artiq/coredevice/ad9912.py
index bd5daa78f..5a4af26b2 100644
--- a/artiq/coredevice/ad9912.py
+++ b/artiq/coredevice/ad9912.py
@@ -1,6 +1,6 @@
 from numpy import int32, int64
 
-from artiq.language.core import KernelInvariant, nac3, kernel, portable
+from artiq.language.core import *
 from artiq.language.units import ms, us, ns
 from artiq.coredevice.ad9912_reg import *
 
@@ -35,7 +35,7 @@ class AD9912:
     chip_select: KernelInvariant[int32]
     pll_n: KernelInvariant[int32]
     ftw_per_hz: KernelInvariant[float]
-    sw: KernelInvariant[TTLOut]
+    sw: KernelInvariant[Option[TTLOut]]
 
     def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
                  pll_n=10):
@@ -45,8 +45,9 @@ class AD9912:
         assert 4 <= chip_select <= 7
         self.chip_select = chip_select
         if sw_device:
-            self.sw = dmgr.get(sw_device)
-            # NAC3TODO: support no sw
+            self.sw = Some(dmgr.get(sw_device))
+        else:
+            self.sw = none
         self.pll_n = pll_n
         sysclk = self.cpld.refclk / [1, 1, 2, 4][self.cpld.clk_div] * pll_n
         assert sysclk <= 1e9
diff --git a/artiq/examples/nac3devices/nac3devices.py b/artiq/examples/nac3devices/nac3devices.py
index c76c4a09a..7bc98738b 100644
--- a/artiq/examples/nac3devices/nac3devices.py
+++ b/artiq/examples/nac3devices/nac3devices.py
@@ -67,7 +67,7 @@ class NAC3Devices(EnvExperiment):
         self.core.break_realtime()
         self.urukul0_cpld.init()
         self.urukul0_ch0.init()
-        self.urukul0_ch0.sw.on()
+        self.urukul0_ch0.sw.unwrap().on()
         for i in range(10):
             self.urukul0_ch0.set((10. + float(i))*MHz)
             self.urukul0_ch0.set_att(6.)