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doc: Warning on Urukul cycle alignment in DMA

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architeuthidae 2024-12-27 13:08:51 +01:00 committed by Sébastien Bourdeauducq
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commit 626c709b4e
1 changed files with 9 additions and 1 deletions
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10
artiq/coredevice/ad9910.py
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@ -534,9 +534,17 @@ class AD9910:
After the SPI transfer, the shared IO update pin is pulsed to After the SPI transfer, the shared IO update pin is pulsed to
activate the data. activate the data.
.. seealso: :meth:`AD9910.set_phase_mode` for a definition of the different .. seealso:: :meth:`AD9910.set_phase_mode` for a definition of the different
phase modes. phase modes.
.. warning::
Deterministic phase control depends on correct alignment of operations
to a 4ns grid (``SYNC_CLK``). This function uses :meth:`~artiq.language.core.now_mu()`
to ensure such alignment automatically. When replayed over DMA, however, the ensuing
event sequence *must* be started at the same offset relative to ``SYNC_CLK``, or
unstable ``SYNC_CLK`` cycle assignment (i.e. inconsistent delays of exactly 4ns) will
result.
:param ftw: Frequency tuning word: 32-bit. :param ftw: Frequency tuning word: 32-bit.
:param pow_: Phase tuning word: 16-bit unsigned. :param pow_: Phase tuning word: 16-bit unsigned.
:param asf: Amplitude scale factor: 14-bit unsigned. :param asf: Amplitude scale factor: 14-bit unsigned.