From 30051133b7ee42d2a36f98aa45ece1cdffb12ea0 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 21 Jan 2019 19:37:33 +0800 Subject: [PATCH] urukul: fix typos --- artiq/coredevice/ad9910.py | 2 +- artiq/coredevice/urukul.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py index 42f6945be..d396c3d44 100644 --- a/artiq/coredevice/ad9910.py +++ b/artiq/coredevice/ad9910.py @@ -615,7 +615,7 @@ class AD9910: This method first locates a valid SYNC_IN delay at zero validation window size (setup/hold margin) by scanning around `search_seed`. It then looks for similar valid delays at successively larger validation - window sizes until none can be found. It then deacreses the validation + window sizes until none can be found. It then decreases the validation window a bit to provide some slack and stability and returns the optimal values. diff --git a/artiq/coredevice/urukul.py b/artiq/coredevice/urukul.py index 723db47fd..e506775c5 100644 --- a/artiq/coredevice/urukul.py +++ b/artiq/coredevice/urukul.py @@ -340,7 +340,7 @@ class CPLD: and align it to the current RTIO timestamp. The SYNC_IN signal is derived from the coarse RTIO clock - and the divider must be a power of two two. + and the divider must be a power of two. Configure ``sync_sel == 0``. :param div: SYNC_IN frequency divider. Must be a power of two.