From 0c408afe8dff13e73b2072c8b54b6331ae4b8e7f Mon Sep 17 00:00:00 2001 From: architeuthidae Date: Fri, 27 Dec 2024 13:08:51 +0100 Subject: [PATCH] doc: Warning on Urukul cycle alignment in DMA --- artiq/coredevice/ad9910.py | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py index 821411b8e..fa0640321 100644 --- a/artiq/coredevice/ad9910.py +++ b/artiq/coredevice/ad9910.py @@ -534,9 +534,17 @@ class AD9910: After the SPI transfer, the shared IO update pin is pulsed to activate the data. - .. seealso: :meth:`AD9910.set_phase_mode` for a definition of the different + .. seealso:: :meth:`AD9910.set_phase_mode` for a definition of the different phase modes. + .. warning:: + Deterministic phase control depends on correct alignment of operations + to a 4ns grid (``SYNC_CLK``). This function uses :meth:`~artiq.language.core.now_mu()` + to ensure such alignment automatically. When replayed over DMA, however, the ensuing + event sequence *must* be started at the same offset relative to ``SYNC_CLK``, or + unstable ``SYNC_CLK`` cycle assignment (i.e. inconsistent delays of exactly 4ns) will + result. + :param ftw: Frequency tuning word: 32-bit. :param pow_: Phase tuning word: 16-bit unsigned. :param asf: Amplitude scale factor: 14-bit unsigned.