pca006132
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  • Joined on 2020-04-27
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pca006132 pushed to l2-cache at pca006132/artiq-zynq 2020-08-21 16:22:37 +08:00
9947b05e97 at least it works
pca006132 pushed to master at M-Labs/compiler-builtins-zynq 2020-08-21 15:30:07 +08:00
6dd42338c6 Added memcpy with neon optimization for zynq.
f4c7940d3b Improve __clzsi2 performance (#366)
f3846bc05d lint: Allow improper_ctypes_definitions (#364)
7b996ca0fa Bump to 0.1.32
f853d6d9b7 Manually patch ret instruction for LVI (#359)
pca006132 created repository M-Labs/compiler-builtins-zynq 2020-08-21 15:25:00 +08:00
pca006132 pushed to master at M-Labs/zynq-rs 2020-08-21 13:35:27 +08:00
bb09d25378 libboard_zynq/ethernet: ethernet fix and config
pca006132 pushed to master at pca006132/zynq-rs 2020-08-21 13:34:57 +08:00
bb09d25378 libboard_zynq/ethernet: ethernet fix and config
a1f859637a experiments: enabled L2 cache
7cb2669c3b Updated cargo dependencies
511c906d4d libcortex_a9/uncached: fixed mmu setting
1ba0aa450f libsupport_zynq/boot: fix cache mainteinance opertaions
Compare 15 commits »
pca006132 pushed to l2-cache at pca006132/zynq-rs 2020-08-20 13:03:15 +08:00
a1f859637a experiments: enabled L2 cache
7cb2669c3b Updated cargo dependencies
511c906d4d libcortex_a9/uncached: fixed mmu setting
1ba0aa450f libsupport_zynq/boot: fix cache mainteinance opertaions
283bc9b810 libcortex_a9: added L2 cache
Compare 10 commits »
pca006132 pushed to l2-cache at pca006132/zynq-rs 2020-08-20 12:05:31 +08:00
3e8c55f7f5 experiments: enabled L2 cache
0939db4bf2 Updated cargo dependencies
78aa52a9ed libcortex_a9/uncached: fixed mmu setting
cddb14b764 libsupport_zynq/boot: fix cache mainteinance opertaions
327817c627 libcortex_a9: added L2 cache
Compare 10 commits »
pca006132 pushed to l2-cache at pca006132/zynq-rs 2020-08-20 12:01:49 +08:00
7dea8f0d6e experiments: enabled L2 cache
0eaf887239 Updated cargo dependencies
e453374532 libcortex_a9/uncached: fixed mmu setting
0fdc41fb8b libsupport_zynq/boot: fix cache mainteinance opertaions
9e182e9883 libcortex_a9: added L2 cache
Compare 15 commits »
pca006132 pushed to l2-cache at pca006132/artiq-zynq 2020-08-18 17:24:19 +08:00
26b0716090 runtime: optimization for rpc
a780de5288 runtime: optimization for rpc
Compare 2 commits »
pca006132 pushed to l2-cache at pca006132/artiq-zynq 2020-08-18 17:22:14 +08:00
a780de5288 runtime: optimization for rpc
899cb01e22 runtime/comms: turn on L2 cache.
2182bcdb9f szl: flush all cache lines instead of all ddr ram.
9a6b8ad161 runtime: uart log level default to info.
1cd53405ba runtime: fixed backtrace when kernel is not loaded.
Compare 18 commits »
pca006132 commented on issue M-Labs/zynq-rs#30 2020-08-14 15:48:50 +08:00
poor Ethernet performance

The problem is fixed by modifying the MMU setting for uncached slice. However, the rx speed is still pretty slow comparing to tx speed. There are also a few changes, like modified the cache flush for rx and prevented duplicates in the waker queue.

Branch:

> python -m unittest test_performance -v
test_kernel_overhead (test_performance.KernelOverheadTest) ... 0.017314874350558965 s
ok
test_device_to_host (test_performance.TransferTest) ... 31.725000159885067 MiB/s
ok
test_device_to_host_array (test_performance.TransferTest) ... 5.5078113984377195 MiB/s
ok
test_host_to_device (test_performance.TransferTest) ... 3.6111348770332103 MiB/s
ok
pca006132 pushed to l2-cache at pca006132/artiq-zynq 2020-08-14 15:41:41 +08:00
ca0cc0476b runtime/comms: turn on L2 cache.
39937b1f1e szl: flush all cache lines instead of all ddr ram.
dc2e44ead7 runtime: uart log level default to info.
f391fc5e69 runtime: fixed backtrace when kernel is not loaded.
13f016088e Updated zynq-rs dependency.
pca006132 pushed to l2-cache at pca006132/zynq-rs 2020-08-14 15:21:37 +08:00
5673d36fc7 libasync: removed duplicated wakers and spaces.
4674807706 libboard_zynq/eth: cache invalidation for rx buffer.
ba21d72185 libcortex_a9/uncached: set as non-shareable memory
67b8186d37 Added L2 cache operations
c69cd9951e Update README and build.sh (#59)
pca006132 renamed repository from zc706 to pca006132/zynq-rs 2020-08-11 15:09:07 +08:00
pca006132 pushed to rtio at pca006132/artiq-zynq 2020-08-11 13:34:00 +08:00
df44eab2bc runtime/rtio_acp: change back to normal sequence.
pca006132 pushed to rtio at pca006132/artiq-zynq 2020-08-11 12:49:56 +08:00
d12bf11de1 runtime/rtio_acp: working
d63f72b098 runtime/kernel: reset rtio after forceful termination.
0f5ff4dbf1 runtime/rtio_acp: use volatile fields
Compare 3 commits »
pca006132 pushed to rtio at pca006132/artiq-zynq 2020-08-10 11:43:38 +08:00
d63f72b098 runtime/kernel: reset rtio after forceful termination.
0f5ff4dbf1 runtime/rtio_acp: use volatile fields
pca006132 pushed to master at pca006132/zynq-rs 2020-08-07 15:11:33 +08:00
fa07bdb681 libcortex_a9/mmu: share ocm3.
4565a75766 experiments: add I2C bitbang EEPROM writing/reading example
16b2df91ca i2c: fix GPIO register mapping, I2C control & EEPROM write operations
f7d3135ec7 i2c: implement EEPROM operations; add CountDown waiting indication
c60230af25 i2c: implement basic i2c bitbanging
Compare 43 commits »
pca006132 pushed to master at pca006132/artiq-zynq 2020-08-07 13:27:00 +08:00
7342736124 szl: reduced binary size.
3a8a025d5f update dependencies, zc706 -> zynq-rs
2f6310f8bd cleanup
8dabc8e6fd runtime: remove access to obsolete i_overflow_reset CSR
1eeee43d64 acpki: implement input interface
Compare 14 commits »
pca006132 pushed to master at M-Labs/artiq-zynq 2020-08-06 14:00:27 +08:00
0354699ae3 runtime/kernel/dma: fixed missing end of buffer marker.