forked from M-Labs/zynq-rs
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No commits in common. "4acee21c05969f7d9a947ba43f60b2c1a60bae55" and "244ccdeac276efcef858f6914fa16c1a157ee0b8" have entirely different histories.
4acee21c05
...
244ccdeac2
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@ -66,7 +66,6 @@ dependencies = [
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"embedded-hal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
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"libcortex_a9 0.0.0",
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"libregister 0.0.0",
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"log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)",
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"nb 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"smoltcp 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"void 1.0.2 (registry+https://github.com/rust-lang/crates.io-index)",
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@ -98,13 +97,14 @@ dependencies = [
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"libboard_zynq 0.0.0",
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"libcortex_a9 0.0.0",
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"libregister 0.0.0",
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"linked_list_allocator 0.8.3 (registry+https://github.com/rust-lang/crates.io-index)",
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"linked_list_allocator 0.8.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)",
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"r0 1.0.0 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "linked_list_allocator"
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version = "0.8.3"
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version = "0.8.2"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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@ -170,7 +170,7 @@ dependencies = [
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"checksum cfg-if 0.1.10 (registry+https://github.com/rust-lang/crates.io-index)" = "4785bdd1c96b2a846b2bd7cc02e86b6b3dbf14e7e53446c4f54c92a361040822"
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"checksum compiler_builtins 0.1.27 (registry+https://github.com/rust-lang/crates.io-index)" = "38f18416546abfbf8d801c555a0e99524453e7214f9cc9107ad49de3d5948ccc"
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"checksum embedded-hal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)" = "ee4908a155094da7723c2d60d617b820061e3b4efcc3d9e293d206a5a76c170b"
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"checksum linked_list_allocator 0.8.3 (registry+https://github.com/rust-lang/crates.io-index)" = "d6b60501dd4c850950bb43f970d544f6ce04e0ca021da2db2538fbe9d923f19e"
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"checksum linked_list_allocator 0.8.2 (registry+https://github.com/rust-lang/crates.io-index)" = "c1070ea54beccbfd3a3987aca6440f94cc1e0b447c2d979d8c7f761e265417e4"
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"checksum log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)" = "14b6052be84e6b71ab17edffc2eeabf5c2c3ae1fdb464aae35ac50c67a44e1f7"
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"checksum managed 0.7.1 (registry+https://github.com/rust-lang/crates.io-index)" = "fdcec5e97041c7f0f1c5b7d93f12e57293c831c646f4cc7a5db59460c7ea8de6"
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"checksum nb 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)" = "b1411551beb3c11dedfb0a90a0fa256b47d28b9ec2cdff34c25a2fa59e45dbdc"
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@ -12,7 +12,7 @@ fn main() {
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.unwrap();
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println!("cargo:rustc-link-search={}", out.display());
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// Only re-run the build script when link.x is changed,
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// Only re-run the build script when memory.x is changed,
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// instead of when any part of the source code changes.
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println!("cargo:rerun-if-changed=link.x");
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}
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@ -49,10 +49,9 @@ let
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name = "${crate}";
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src = ./.;
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crateSubdir = crate;
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cargoSha256 = "0xlynsr94dyv0g41qwk5490w3wnzd5g70msaih6mcbgr3v4s2q34";
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cargoSha256 = "0wqsxbcphcf240mqfglckl0lz82f19g1jlcf3xk73aflpyxk5pmm";
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cargoFeatures = features;
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doCheck = false;
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dontFixup = true;
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};
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in {
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inherit pkgs rustPlatform rustcSrc gcc;
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@ -1,68 +0,0 @@
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ENTRY(_boot_cores);
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/* Provide some defaults */
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PROVIDE(Reset = _boot_cores);
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PROVIDE(UndefinedInstruction = Reset);
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PROVIDE(SoftwareInterrupt = Reset);
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PROVIDE(PrefetchAbort = Reset);
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PROVIDE(DataAbort = Reset);
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PROVIDE(ReservedException = Reset);
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PROVIDE(IRQ = Reset);
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PROVIDE(FIQ = Reset);
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MEMORY
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{
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/* 256 kB On-Chip Memory */
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OCM : ORIGIN = 0, LENGTH = 0x30000
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OCM3 : ORIGIN = 0xFFFF0000, LENGTH = 0x10000
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}
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SECTIONS
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{
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.text :
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{
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KEEP(*(.text.exceptions));
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*(.text.boot);
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*(.text .text.*);
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} > OCM
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.rodata : ALIGN(4)
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{
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*(.rodata .rodata.*);
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} > OCM
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.data : ALIGN(4)
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{
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*(.data .data.*);
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} > OCM
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.bss (NOLOAD) : ALIGN(4)
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{
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__bss_start = .;
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*(.bss .bss.*);
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. = ALIGN(4);
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__bss_end = .;
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} > OCM
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.stack1 (NOLOAD) : ALIGN(8) {
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__stack1_end = .;
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. += 0x200;
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__stack1_start = .;
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} > OCM
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.stack0 (NOLOAD) : ALIGN(8) {
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__stack0_end = .;
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. = ORIGIN(OCM) + LENGTH(OCM) - 8;
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__stack0_start = .;
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} > OCM
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/DISCARD/ :
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{
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/* Unused exception related info that only wastes space */
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*(.ARM.exidx);
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*(.ARM.exidx.*);
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*(.ARM.extab.*);
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}
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}
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ASSERT(SIZEOF(.stack0) >= 0x1000, "less than 4 KB left for stack");
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@ -6,6 +6,7 @@ extern crate alloc;
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use core::{mem::transmute, task::Poll};
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use alloc::{borrow::ToOwned, collections::BTreeMap, format};
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use log::info;
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use embedded_hal::timer::CountDown;
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use libregister::RegisterR;
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use libcortex_a9::{mutex::Mutex, sync_channel::{self, sync_channel}};
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use libboard_zynq::{
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@ -16,6 +17,8 @@ use libboard_zynq::{
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wire::{EthernetAddress, IpAddress, IpCidr},
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iface::{NeighborCache, EthernetInterfaceBuilder, Routes},
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time::Instant,
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socket::SocketSet,
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socket::{TcpSocket, TcpSocketBuffer},
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},
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time::Milliseconds,
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};
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@ -29,12 +32,14 @@ mod ps7_init;
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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static mut STACK_CORE1: [u32; 512] = [0; 512];
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#[no_mangle]
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pub fn main_core0() {
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// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
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println!("\nzc706 main");
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libboard_zynq::logger::init().unwrap();
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libsupport_zynq::logger::init().unwrap();
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log::set_max_level(log::LevelFilter::Trace);
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info!("Boot mode: {:?}", zynq::slcr::RegisterBlock::new().boot_mode.read().boot_mode_pins());
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@ -44,7 +49,7 @@ pub fn main_core0() {
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#[cfg(feature = "target_cora_z7_10")]
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const CPU_FREQ: u32 = 650_000_000;
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info!("Setup clock sources...");
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println!("Setup clock sources...");
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ArmPll::setup(2 * CPU_FREQ);
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Clocks::set_cpu_freq(CPU_FREQ);
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#[cfg(feature = "target_zc706")]
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@ -52,9 +57,9 @@ pub fn main_core0() {
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IoPll::setup(1_000_000_000);
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libboard_zynq::stdio::drop_uart();
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}
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info!("PLLs set up");
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println!("PLLs set up");
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let clocks = zynq::clocks::Clocks::get();
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info!("CPU Clocks: {}/{}/{}/{}", clocks.cpu_6x4x(), clocks.cpu_3x2x(), clocks.cpu_2x(), clocks.cpu_1x());
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println!("CPU Clocks: {}/{}/{}/{}", clocks.cpu_6x4x(), clocks.cpu_3x2x(), clocks.cpu_2x(), clocks.cpu_1x());
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let mut flash = zynq::flash::Flash::new(200_000_000).linear_addressing_mode();
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let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) };
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@ -74,7 +79,6 @@ pub fn main_core0() {
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ddr.memtest();
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ram::init_alloc_ddr(&mut ddr);
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#[cfg(dev)]
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for i in 0..=1 {
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let mut flash_io = flash.manual_mode(i);
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// println!("rdcr={:02X}", flash_io.rdcr());
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@ -107,13 +111,41 @@ pub fn main_core0() {
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flash_io.erase(0);
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});
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flash_io.write_enabled(|flash_io| {
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flash_io.program(0, [0x23054223; 0x100 >> 2].iter().cloned());
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flash_io.program(0, [0x23054223; (0x100 >> 2)].iter().cloned());
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});
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flash = flash_io.stop();
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}
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let core1 = boot::Core1::start();
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let (mut tx, mut rx) = sync_channel::sync_channel(0);
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task::spawn(async move {
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println!("outer task");
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while let Some(item) = *rx.async_recv().await {
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println!("received {}", item);
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}
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});
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task::spawn(async {
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for i in 1..=3 {
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println!("outer task2: {}", i);
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task::r#yield().await;
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}
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});
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task::block_on(async {
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task::spawn(async {
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println!("inner task");
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});
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|
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for i in 1..=10 {
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println!("yield {}", i);
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task::r#yield().await;
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tx.async_send(Some(i)).await;
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}
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tx.async_send(None).await;
|
||||
});
|
||||
|
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let core1_stack = unsafe { &mut STACK_CORE1[..] };
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println!("{} bytes stack for core1", core1_stack.len());
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let core1 = boot::Core1::start(core1_stack);
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let (mut core1_req, rx) = sync_channel(10);
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*CORE1_REQ.lock() = Some(rx);
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@ -128,6 +160,13 @@ pub fn main_core0() {
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});
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core1.disable();
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|
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libcortex_a9::asm::dsb();
|
||||
print!("Core1 stack [{:08X}..{:08X}]:", &core1.stack[0] as *const _ as u32, &core1.stack[core1.stack.len() - 1] as *const _ as u32);
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||||
for w in core1.stack {
|
||||
print!(" {:08X}", w);
|
||||
}
|
||||
println!(".");
|
||||
|
||||
let eth = zynq::eth::Eth::default(HWADDR.clone());
|
||||
println!("Eth on");
|
||||
|
||||
|
|
@ -150,13 +189,23 @@ pub fn main_core0() {
|
|||
unsafe { transmute(tx_descs.as_mut_slice()) },
|
||||
unsafe { transmute(tx_buffers.as_mut_slice()) },
|
||||
);
|
||||
// loop {
|
||||
// match eth.recv_next() {
|
||||
// Ok(None) => {},
|
||||
// Ok(Some(pkt)) => println!("received {} bytes", pkt.len()),
|
||||
// Err(e) => println!("e: {:?}", e),
|
||||
// }
|
||||
// }
|
||||
|
||||
println!("iface...");
|
||||
let ethernet_addr = EthernetAddress(HWADDR);
|
||||
// IP stack
|
||||
let local_addr = IpAddress::v4(192, 168, 1, 51);
|
||||
let mut ip_addrs = [IpCidr::new(local_addr, 24)];
|
||||
let routes = Routes::new(BTreeMap::new());
|
||||
let neighbor_cache = NeighborCache::new(BTreeMap::new());
|
||||
let mut routes_storage = vec![None; 4];
|
||||
let routes = Routes::new(/*BTreeMap::new()*/ &mut routes_storage[..]);
|
||||
let mut neighbor_storage = vec![None; 256];
|
||||
let neighbor_cache = NeighborCache::new(&mut neighbor_storage[..]);
|
||||
let mut iface = EthernetInterfaceBuilder::new(&mut eth)
|
||||
.ethernet_addr(ethernet_addr)
|
||||
.ip_addrs(&mut ip_addrs[..])
|
||||
|
|
@ -164,8 +213,8 @@ pub fn main_core0() {
|
|||
.neighbor_cache(neighbor_cache)
|
||||
.finalize();
|
||||
|
||||
ps7_init::report_differences();
|
||||
|
||||
// TODO: compare with ps7_init
|
||||
|
||||
Sockets::init(32);
|
||||
/// `chargen`
|
||||
const TCP_PORT: u16 = 19;
|
||||
|
|
@ -195,20 +244,20 @@ pub fn main_core0() {
|
|||
None =>
|
||||
stream.send("I had trouble reading your name.\n".bytes()).await?,
|
||||
}
|
||||
let _ = stream.flush().await;
|
||||
stream.flush().await;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
let counter = alloc::rc::Rc::new(core::cell::RefCell::new(0));
|
||||
let mut counter = alloc::rc::Rc::new(core::cell::RefCell::new(0));
|
||||
task::spawn(async move {
|
||||
while let Ok(stream) = TcpStream::accept(TCP_PORT, 2048, 2408).await {
|
||||
while let stream = TcpStream::accept(TCP_PORT, 2048, 2408).await.unwrap() {
|
||||
let counter = counter.clone();
|
||||
task::spawn(async move {
|
||||
*counter.borrow_mut() += 1;
|
||||
println!("Serving {} connections", *counter.borrow());
|
||||
handle_connection(stream)
|
||||
.await
|
||||
.unwrap_or_else(|e| println!("Connection: {:?}", e));
|
||||
.map_err(|e| println!("Connection: {:?}", e));
|
||||
*counter.borrow_mut() -= 1;
|
||||
println!("Now serving {} connections", *counter.borrow());
|
||||
});
|
||||
|
|
@ -223,7 +272,7 @@ pub fn main_core0() {
|
|||
let timestamp = timer.get_us();
|
||||
let seconds = timestamp / 1_000_000;
|
||||
let micros = timestamp % 1_000_000;
|
||||
info!("time: {:6}.{:06}s", seconds, micros);
|
||||
println!("time: {:6}.{:06}s", seconds, micros);
|
||||
}
|
||||
});
|
||||
|
||||
|
|
@ -244,7 +293,7 @@ pub fn main_core1() {
|
|||
while req.is_none() {
|
||||
req = CORE1_REQ.lock().take();
|
||||
}
|
||||
let req = req.unwrap();
|
||||
let mut req = req.unwrap();
|
||||
let mut res = None;
|
||||
while res.is_none() {
|
||||
res = CORE1_RES.lock().take();
|
||||
|
|
|
|||
|
|
@ -15,7 +15,6 @@ bit_field = "0.10"
|
|||
embedded-hal = "0.2"
|
||||
nb = "0.1"
|
||||
void = { version = "1", default-features = false }
|
||||
log = "0.4"
|
||||
libregister = { path = "../libregister" }
|
||||
libcortex_a9 = { path = "../libcortex_a9" }
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
use log::debug;
|
||||
use libregister::{RegisterR, RegisterW, RegisterRW};
|
||||
use super::slcr;
|
||||
|
||||
|
|
@ -49,8 +48,6 @@ pub trait ClockSource {
|
|||
u32::from(pll_ctrl.read().pll_fdiv()) * PS_CLK
|
||||
}
|
||||
|
||||
fn name() -> &'static str;
|
||||
|
||||
/// Zynq-7000 AP SoC Technical Reference Manual:
|
||||
/// 25.10.4 PLLs
|
||||
fn setup(target_freq: u32) {
|
||||
|
|
@ -61,7 +58,6 @@ pub trait ClockSource {
|
|||
.expect("PLL_FDIV_LOCK_PARAM")
|
||||
.1.clone();
|
||||
|
||||
debug!("Set {} to {} Hz", Self::name(), target_freq);
|
||||
slcr::RegisterBlock::unlocked(|slcr| {
|
||||
let (pll_ctrl, pll_cfg, pll_status) = Self::pll_regs(slcr);
|
||||
|
||||
|
|
@ -112,10 +108,6 @@ impl ClockSource for ArmPll {
|
|||
fn pll_locked(pll_status: &mut crate::slcr::PllStatus) -> bool {
|
||||
pll_status.read().arm_pll_lock()
|
||||
}
|
||||
|
||||
fn name() -> &'static str {
|
||||
&"ARM_PLL"
|
||||
}
|
||||
}
|
||||
|
||||
/// DDR PLL: Recommended clock for the DDR DRAM controller and AXI_HP interfaces
|
||||
|
|
@ -138,10 +130,6 @@ impl ClockSource for DdrPll {
|
|||
fn pll_locked(pll_status: &mut crate::slcr::PllStatus) -> bool {
|
||||
pll_status.read().ddr_pll_lock()
|
||||
}
|
||||
|
||||
fn name() -> &'static str {
|
||||
&"DDR_PLL"
|
||||
}
|
||||
}
|
||||
|
||||
/// I/O PLL: Recommended clock for I/O peripherals
|
||||
|
|
@ -165,8 +153,4 @@ impl ClockSource for IoPll {
|
|||
fn pll_locked(pll_status: &mut crate::slcr::PllStatus) -> bool {
|
||||
pll_status.read().io_pll_lock()
|
||||
}
|
||||
|
||||
fn name() -> &'static str {
|
||||
&"IO_PLL"
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,4 @@
|
|||
use libregister::{RegisterR, RegisterW, RegisterRW};
|
||||
use log::{debug, info, error};
|
||||
use crate::{print, println};
|
||||
use super::slcr::{self, DdriobVrefSel};
|
||||
use super::clocks::{Clocks, source::{DdrPll, ClockSource}};
|
||||
|
|
@ -39,9 +38,11 @@ impl DdrRam {
|
|||
DdrPll::setup(2 * DDR_FREQ);
|
||||
|
||||
let clocks = Clocks::get();
|
||||
println!("Clocks: {:?}", clocks);
|
||||
|
||||
let ddr3x_clk_divisor = 2;
|
||||
let ddr2x_clk_divisor = 3;
|
||||
debug!("DDR 3x/2x clocks: {}/{}", clocks.ddr / u32::from(ddr3x_clk_divisor), clocks.ddr / u32::from(ddr2x_clk_divisor));
|
||||
println!("DDR 3x/2x clocks: {}/{}", clocks.ddr / u32::from(ddr3x_clk_divisor), clocks.ddr / u32::from(ddr2x_clk_divisor));
|
||||
|
||||
slcr::RegisterBlock::unlocked(|slcr| {
|
||||
slcr.ddr_clk_ctrl.write(
|
||||
|
|
@ -62,7 +63,7 @@ impl DdrRam {
|
|||
.max(1).min(63) as u8;
|
||||
let divisor1 = ((DCI_FREQ - 1 + clocks.ddr) / DCI_FREQ / u32::from(divisor0))
|
||||
.max(1).min(63) as u8;
|
||||
debug!("DDR DCI clock: {} Hz", clocks.ddr / u32::from(divisor0) / u32::from(divisor1));
|
||||
println!("DDR DCI clock: {} Hz", clocks.ddr / u32::from(divisor0) / u32::from(divisor1));
|
||||
|
||||
slcr::RegisterBlock::unlocked(|slcr| {
|
||||
// Step 1.
|
||||
|
|
@ -225,7 +226,7 @@ impl DdrRam {
|
|||
let patterns: &'static [u32] = &[0xffff_ffff, 0x5555_5555, 0xaaaa_aaaa, 0];
|
||||
let mut expected = None;
|
||||
for (i, pattern) in patterns.iter().enumerate() {
|
||||
info!("memtest phase {} (status: {:?})", i, self.status());
|
||||
println!("memtest phase {} (status: {:?})", i, self.status());
|
||||
|
||||
for megabyte in 0..=(slice.len() / (1024 * 1024)) {
|
||||
let start = megabyte * 1024 * 1024 / 4;
|
||||
|
|
@ -234,7 +235,7 @@ impl DdrRam {
|
|||
expected.map(|expected| {
|
||||
let read: u32 = *b;
|
||||
if read != expected {
|
||||
error!("{:08X}: expected {:08X}, read {:08X}", b as *mut _ as usize, expected, read);
|
||||
println!("{:08X}: expected {:08X}, read {:08X}", b as *mut _ as usize, expected, read);
|
||||
}
|
||||
});
|
||||
*b = *pattern;
|
||||
|
|
|
|||
|
|
@ -26,18 +26,12 @@ impl DevC {
|
|||
})
|
||||
}
|
||||
|
||||
pub fn is_done(&self) -> bool {
|
||||
// Note: contrary to what the TRM says, this appears to be simply
|
||||
// the state of the DONE signal.
|
||||
self.regs.int_sts.read().ixr_pcfg_done()
|
||||
}
|
||||
|
||||
pub fn program(&mut self) {
|
||||
slcr::RegisterBlock::unlocked(|slcr| {
|
||||
slcr.init_preload_fpga();
|
||||
});
|
||||
|
||||
while !self.is_done() {}
|
||||
while !self.regs.int_sts.read().ixr_pcfg_done() {}
|
||||
|
||||
slcr::RegisterBlock::unlocked(|slcr| {
|
||||
slcr.init_postload_fpga();
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
use core::ops::{Deref, DerefMut};
|
||||
use log::{error, info, warn};
|
||||
use libregister::*;
|
||||
use crate::println;
|
||||
use super::slcr;
|
||||
use super::clocks::Clocks;
|
||||
|
||||
|
|
@ -389,7 +389,7 @@ impl<'r, 'rx, 'tx: 'a, 'a> smoltcp::phy::Device<'a> for &mut Eth<'r, rx::DescLis
|
|||
None
|
||||
}
|
||||
Err(e) => {
|
||||
error!("eth recv error: {:?}", e);
|
||||
println!("eth recv error: {:?}", e);
|
||||
None
|
||||
}
|
||||
}
|
||||
|
|
@ -555,7 +555,7 @@ impl<'r> EthInner<'r> {
|
|||
if self.link != link {
|
||||
match &link {
|
||||
Some(link) => {
|
||||
info!("eth: got {:?}", link);
|
||||
println!("eth: got {:?}", link);
|
||||
|
||||
use phy::LinkSpeed::*;
|
||||
let txclock = match link.speed {
|
||||
|
|
@ -573,7 +573,7 @@ impl<'r> EthInner<'r> {
|
|||
);
|
||||
}
|
||||
None => {
|
||||
warn!("eth: link lost");
|
||||
println!("eth: link lost");
|
||||
phy.modify_control(self, |control|
|
||||
control.set_autoneg_enable(true)
|
||||
.set_restart_autoneg(true)
|
||||
|
|
|
|||
|
|
@ -1,9 +1,8 @@
|
|||
//! Quad-SPI Flash Controller
|
||||
|
||||
use core::marker::PhantomData;
|
||||
use log::{error, info, warn};
|
||||
use libregister::{RegisterR, RegisterW, RegisterRW};
|
||||
use crate::{print, println};
|
||||
use core::marker::PhantomData;
|
||||
use libregister::{RegisterR, RegisterW, RegisterRW};
|
||||
use super::slcr;
|
||||
use super::clocks::source::{IoPll, ClockSource};
|
||||
|
||||
|
|
@ -423,17 +422,17 @@ impl Flash<Manual> {
|
|||
let sr1 = self.wait_while_sr1_zeroed();
|
||||
|
||||
if sr1.e_err() {
|
||||
error!("E_ERR");
|
||||
println!("E_ERR");
|
||||
} else if sr1.p_err() {
|
||||
error!("P_ERR");
|
||||
println!("P_ERR");
|
||||
} else if sr1.wip() {
|
||||
info!("Erase in progress");
|
||||
print!("Erase in progress");
|
||||
while self.read_reg::<SR1>().wip() {
|
||||
print!(".");
|
||||
}
|
||||
println!("");
|
||||
} else {
|
||||
warn!("erased? sr1={:02X}", sr1.inner);
|
||||
println!("erased? sr1={:02X}", sr1.inner);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -449,17 +448,17 @@ impl Flash<Manual> {
|
|||
let sr1 = self.read_reg::<SR1>();
|
||||
|
||||
if sr1.e_err() {
|
||||
error!("E_ERR");
|
||||
println!("E_ERR");
|
||||
} else if sr1.p_err() {
|
||||
error!("P_ERR");
|
||||
println!("P_ERR");
|
||||
} else if sr1.wip() {
|
||||
info!("Program in progress");
|
||||
println!("Program in progress");
|
||||
while self.read_reg::<SR1>().wip() {
|
||||
print!(".");
|
||||
}
|
||||
println!("");
|
||||
} else {
|
||||
warn!("programmed? sr1={:02X}", sr1.inner);
|
||||
println!("programmed? sr1={:02X}", sr1.inner);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -17,5 +17,4 @@ pub mod flash;
|
|||
pub mod dmac;
|
||||
pub mod time;
|
||||
pub mod timer;
|
||||
pub mod sdio;
|
||||
pub mod logger;
|
||||
pub mod sdio;
|
||||
|
|
@ -63,7 +63,6 @@ macro_rules! println {
|
|||
let mut uart = $crate::stdio::get_uart();
|
||||
let _ = write!(uart, $($arg)*);
|
||||
let _ = write!(uart, "\n");
|
||||
// flush after the newline
|
||||
while !uart.tx_idle() {}
|
||||
while !uart.tx_fifo_empty() {}
|
||||
})
|
||||
}
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ pub struct GlobalTimer {
|
|||
impl GlobalTimer {
|
||||
/// Get the potentially uninitialized timer
|
||||
pub unsafe fn get() -> GlobalTimer {
|
||||
let regs = mpcore::RegisterBlock::new();
|
||||
let mut regs = mpcore::RegisterBlock::new();
|
||||
GlobalTimer { regs }
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -192,14 +192,15 @@ impl Uart {
|
|||
self.regs.channel_sts.read().txfull()
|
||||
}
|
||||
|
||||
pub fn tx_idle(&self) -> bool {
|
||||
let status = self.regs.channel_sts.read();
|
||||
status.txempty() && !status.tactive()
|
||||
pub fn tx_fifo_empty(&self) -> bool {
|
||||
self.regs.channel_sts.read().txempty()
|
||||
}
|
||||
}
|
||||
|
||||
impl fmt::Write for Uart {
|
||||
fn write_str(&mut self, s: &str) -> Result<(), fmt::Error> {
|
||||
while !self.tx_fifo_empty() {}
|
||||
|
||||
for b in s.bytes() {
|
||||
self.write_byte(b);
|
||||
}
|
||||
|
|
@ -221,7 +222,7 @@ impl embedded_hal::serial::Write<u8> for Uart {
|
|||
}
|
||||
|
||||
fn flush(&mut self) -> nb::Result<(), Void> {
|
||||
if self.tx_idle() {
|
||||
if self.tx_fifo_empty() {
|
||||
Ok(())
|
||||
} else {
|
||||
Err(nb::Error::WouldBlock)
|
||||
|
|
|
|||
|
|
@ -1,35 +1,35 @@
|
|||
/// The classic no-op
|
||||
#[inline]
|
||||
pub fn nop() {
|
||||
unsafe { llvm_asm!("nop" :::: "volatile") }
|
||||
unsafe { asm!("nop" :::: "volatile") }
|
||||
}
|
||||
|
||||
/// Wait For Event
|
||||
#[inline]
|
||||
pub fn wfe() {
|
||||
unsafe { llvm_asm!("wfe" :::: "volatile") }
|
||||
unsafe { asm!("wfe" :::: "volatile") }
|
||||
}
|
||||
|
||||
/// Send Event
|
||||
#[inline]
|
||||
pub fn sev() {
|
||||
unsafe { llvm_asm!("sev" :::: "volatile") }
|
||||
unsafe { asm!("sev" :::: "volatile") }
|
||||
}
|
||||
|
||||
/// Data Memory Barrier
|
||||
#[inline]
|
||||
pub fn dmb() {
|
||||
unsafe { llvm_asm!("dmb" :::: "volatile") }
|
||||
unsafe { asm!("dmb" :::: "volatile") }
|
||||
}
|
||||
|
||||
/// Data Synchronization Barrier
|
||||
#[inline]
|
||||
pub fn dsb() {
|
||||
unsafe { llvm_asm!("dsb" :::: "volatile") }
|
||||
unsafe { asm!("dsb" :::: "volatile") }
|
||||
}
|
||||
|
||||
/// Instruction Synchronization Barrier
|
||||
#[inline]
|
||||
pub fn isb() {
|
||||
unsafe { llvm_asm!("isb" :::: "volatile") }
|
||||
unsafe { asm!("isb" :::: "volatile") }
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
#[inline(always)]
|
||||
pub fn tlbiall() {
|
||||
unsafe {
|
||||
llvm_asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
|
||||
asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -10,7 +10,7 @@ pub fn tlbiall() {
|
|||
#[inline(always)]
|
||||
pub fn iciallu() {
|
||||
unsafe {
|
||||
llvm_asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
|
||||
asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -18,7 +18,7 @@ pub fn iciallu() {
|
|||
#[inline(always)]
|
||||
pub fn bpiall() {
|
||||
unsafe {
|
||||
llvm_asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
|
||||
asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -26,7 +26,7 @@ pub fn bpiall() {
|
|||
#[inline(always)]
|
||||
pub fn dccsw(setway: u32) {
|
||||
unsafe {
|
||||
llvm_asm!("mcr p15, 0, $0, c7, c10, 2" :: "r" (setway) :: "volatile");
|
||||
asm!("mcr p15, 0, $0, c7, c10, 2" :: "r" (setway) :: "volatile");
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -38,7 +38,7 @@ pub fn dcisw(setway: u32) {
|
|||
// also see example code (for DCCISW, but DCISW will be
|
||||
// analogous) "Example code for cache maintenance operations"
|
||||
// on pages B2-1286 and B2-1287.
|
||||
llvm_asm!("mcr p15, 0, $0, c7, c6, 2" :: "r" (setway) :: "volatile");
|
||||
asm!("mcr p15, 0, $0, c7, c6, 2" :: "r" (setway) :: "volatile");
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -58,7 +58,7 @@ pub fn dciall() {
|
|||
|
||||
// select L1 data cache
|
||||
unsafe {
|
||||
llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
|
||||
asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
|
||||
}
|
||||
|
||||
// Invalidate entire D-Cache by iterating every set and every way
|
||||
|
|
@ -101,7 +101,7 @@ fn slice_cache_line_addrs<T>(slice: &[T]) -> impl Iterator<Item = usize> {
|
|||
#[inline(always)]
|
||||
pub fn dccimvac(addr: usize) {
|
||||
unsafe {
|
||||
llvm_asm!("mcr p15, 0, $0, c7, c14, 1" :: "r" (addr) :: "volatile");
|
||||
asm!("mcr p15, 0, $0, c7, c14, 1" :: "r" (addr) :: "volatile");
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -122,7 +122,7 @@ pub fn dcci_slice<T>(slice: &mut [T]) {
|
|||
#[inline(always)]
|
||||
pub fn dccmvac(addr: usize) {
|
||||
unsafe {
|
||||
llvm_asm!("mcr p15, 0, $0, c7, c10, 1" :: "r" (addr) :: "volatile");
|
||||
asm!("mcr p15, 0, $0, c7, c10, 1" :: "r" (addr) :: "volatile");
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -148,7 +148,7 @@ pub fn dcc_slice<T>(slice: &[T]) {
|
|||
/// affecting more data than intended.
|
||||
#[inline(always)]
|
||||
pub unsafe fn dcimvac(addr: usize) {
|
||||
llvm_asm!("mcr p15, 0, $0, c7, c6, 1" :: "r" (addr) :: "volatile");
|
||||
asm!("mcr p15, 0, $0, c7, c6, 1" :: "r" (addr) :: "volatile");
|
||||
}
|
||||
|
||||
/// Data cache clean and invalidate for an object.
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#![no_std]
|
||||
#![feature(llvm_asm, global_asm)]
|
||||
#![feature(asm, global_asm)]
|
||||
#![feature(never_type)]
|
||||
|
||||
extern crate alloc;
|
||||
|
|
|
|||
|
|
@ -94,11 +94,16 @@ impl L1Entry {
|
|||
}
|
||||
|
||||
const L1_TABLE_SIZE: usize = 4096;
|
||||
static mut L1_TABLE: L1Table = L1Table {
|
||||
#[doc(hidden)]
|
||||
#[link_section = ".bss.l1_table"]
|
||||
#[no_mangle]
|
||||
pub static mut l1_table: L1Table = L1Table {
|
||||
table: [L1Entry(0); L1_TABLE_SIZE]
|
||||
};
|
||||
|
||||
#[repr(C, align(16384))]
|
||||
/// The `#[repr(align(16384))]` is unfortunately ineffective. Hence we
|
||||
/// require explicit linking to a region defined in the linker script.
|
||||
#[repr(align(16384))]
|
||||
pub struct L1Table {
|
||||
table: [L1Entry; L1_TABLE_SIZE]
|
||||
}
|
||||
|
|
@ -106,7 +111,7 @@ pub struct L1Table {
|
|||
impl L1Table {
|
||||
pub fn get() -> &'static mut Self {
|
||||
unsafe {
|
||||
&mut L1_TABLE
|
||||
&mut l1_table
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ macro_rules! def_reg_r {
|
|||
#[inline]
|
||||
fn read(&self) -> Self::R {
|
||||
let mut value: u32;
|
||||
unsafe { llvm_asm!($asm_instr : "=r" (value) ::: "volatile") }
|
||||
unsafe { asm!($asm_instr : "=r" (value) ::: "volatile") }
|
||||
value.into()
|
||||
}
|
||||
}
|
||||
|
|
@ -26,7 +26,7 @@ macro_rules! def_reg_w {
|
|||
#[inline]
|
||||
fn write(&mut self, value: Self::W) {
|
||||
let value: u32 = value.into();
|
||||
unsafe { llvm_asm!($asm_instr :: "r" (value) :: "volatile") }
|
||||
unsafe { asm!($asm_instr :: "r" (value) :: "volatile") }
|
||||
}
|
||||
|
||||
#[inline]
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@ target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10"]
|
|||
[dependencies]
|
||||
r0 = "1"
|
||||
compiler_builtins = "0.1"
|
||||
log = "0.4"
|
||||
linked_list_allocator = { version = "0.8", default-features = false }
|
||||
libregister = { path = "../libregister" }
|
||||
libcortex_a9 = { path = "../libcortex_a9" }
|
||||
|
|
|
|||
|
|
@ -9,13 +9,13 @@ use libboard_zynq::{slcr, mpcore};
|
|||
extern "C" {
|
||||
static mut __bss_start: u32;
|
||||
static mut __bss_end: u32;
|
||||
static mut __stack0_start: u32;
|
||||
static mut __stack1_start: u32;
|
||||
static mut __stack_start: u32;
|
||||
fn main_core0();
|
||||
fn main_core1();
|
||||
}
|
||||
|
||||
static mut CORE1_ENABLED: VolatileCell<bool> = VolatileCell::new(false);
|
||||
/// `0` means: wait for initialization by core0
|
||||
static mut CORE1_STACK: VolatileCell<u32> = VolatileCell::new(0);
|
||||
|
||||
#[link_section = ".text.boot"]
|
||||
#[no_mangle]
|
||||
|
|
@ -25,14 +25,15 @@ pub unsafe extern "C" fn _boot_cores() -> ! {
|
|||
|
||||
match MPIDR.read() & CORE_MASK {
|
||||
0 => {
|
||||
SP.write(&mut __stack0_start as *mut _ as u32);
|
||||
SP.write(&mut __stack_start as *mut _ as u32);
|
||||
boot_core0();
|
||||
}
|
||||
1 => {
|
||||
while !CORE1_ENABLED.get() {
|
||||
while CORE1_STACK.get() == 0 {
|
||||
asm::wfe();
|
||||
}
|
||||
SP.write(&mut __stack1_start as *mut _ as u32);
|
||||
|
||||
SP.write(CORE1_STACK.get());
|
||||
boot_core1();
|
||||
}
|
||||
_ => unreachable!(),
|
||||
|
|
@ -103,12 +104,18 @@ fn l1_cache_init() {
|
|||
dciall();
|
||||
}
|
||||
|
||||
pub struct Core1 {
|
||||
pub struct Core1<S: AsMut<[u32]>> {
|
||||
pub stack: S,
|
||||
}
|
||||
|
||||
impl Core1 {
|
||||
impl<S: AsMut<[u32]>> Core1<S> {
|
||||
/// Reset and start core1
|
||||
pub fn start() -> Self {
|
||||
///
|
||||
/// The stack must not be in OCM because core1 still has to
|
||||
/// initialize its MMU before it can access DDR.
|
||||
pub fn start(stack: S) -> Self {
|
||||
let mut core = Core1 { stack };
|
||||
|
||||
// reset and stop (safe to repeat)
|
||||
slcr::RegisterBlock::unlocked(|slcr| {
|
||||
slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(true));
|
||||
|
|
@ -116,13 +123,15 @@ impl Core1 {
|
|||
slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
|
||||
});
|
||||
|
||||
let stack = core.stack.as_mut();
|
||||
let stack_start = &mut stack[stack.len() - 1];
|
||||
unsafe {
|
||||
CORE1_ENABLED.set(true);
|
||||
CORE1_STACK.set(stack_start as *mut _ as u32);
|
||||
}
|
||||
// Ensure stack pointer has been written to cache
|
||||
asm::dmb();
|
||||
// Flush cache-line
|
||||
cache::dccmvac(unsafe { &CORE1_ENABLED } as *const _ as usize);
|
||||
cache::dccmvac(unsafe { &CORE1_STACK } as *const _ as usize);
|
||||
|
||||
// wake up core1
|
||||
slcr::RegisterBlock::unlocked(|slcr| {
|
||||
|
|
@ -130,12 +139,12 @@ impl Core1 {
|
|||
slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_clkstop1(false));
|
||||
});
|
||||
|
||||
Core1 {}
|
||||
core
|
||||
}
|
||||
|
||||
pub fn disable(&self) {
|
||||
unsafe {
|
||||
CORE1_ENABLED.set(false);
|
||||
CORE1_STACK.set(0);
|
||||
}
|
||||
self.restart();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -10,4 +10,5 @@ pub extern crate compiler_builtins;
|
|||
pub mod boot;
|
||||
mod abort;
|
||||
mod panic;
|
||||
pub mod logger;
|
||||
pub mod ram;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
//! A logger for the `log` crate
|
||||
|
||||
use crate::{println, stdio, timer::GlobalTimer};
|
||||
use libboard_zynq::{println, stdio, timer::GlobalTimer};
|
||||
|
||||
pub static LOGGER: Logger = Logger;
|
||||
|
||||
|
|
@ -29,6 +29,6 @@ impl log::Log for Logger {
|
|||
}
|
||||
fn flush(&self) {
|
||||
let uart = stdio::get_uart();
|
||||
while !uart.tx_idle() {}
|
||||
while !uart.tx_fifo_empty() {}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
ENTRY(_boot_cores);
|
||||
|
||||
STACK_SIZE = 0x8000;
|
||||
|
||||
/* Provide some defaults */
|
||||
PROVIDE(Reset = _boot_cores);
|
||||
PROVIDE(UndefinedInstruction = Reset);
|
||||
PROVIDE(SoftwareInterrupt = Reset);
|
||||
PROVIDE(PrefetchAbort = Reset);
|
||||
PROVIDE(DataAbort = Reset);
|
||||
PROVIDE(ReservedException = Reset);
|
||||
PROVIDE(IRQ = Reset);
|
||||
PROVIDE(FIQ = Reset);
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* 256 kB On-Chip Memory */
|
||||
OCM : ORIGIN = 0, LENGTH = 0x30000
|
||||
OCM3 : ORIGIN = 0xFFFF0000, LENGTH = 0x10000
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.text.exceptions));
|
||||
*(.text.boot);
|
||||
*(.text .text.*);
|
||||
} > OCM
|
||||
|
||||
.rodata : ALIGN(4)
|
||||
{
|
||||
*(.rodata .rodata.*);
|
||||
} > OCM
|
||||
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
*(.data .data.*);
|
||||
} > OCM
|
||||
|
||||
.bss (NOLOAD) : ALIGN(0x4000)
|
||||
{
|
||||
/* Aligned to 16 kB */
|
||||
KEEP(*(.bss.l1_table));
|
||||
*(.bss .bss.*);
|
||||
. = ALIGN(4);
|
||||
} > OCM
|
||||
__bss_start = ADDR(.bss);
|
||||
__bss_end = ADDR(.bss) + SIZEOF(.bss);
|
||||
|
||||
.stack (NOLOAD) : ALIGN(0x1000) {
|
||||
. += STACK_SIZE;
|
||||
} > OCM
|
||||
__stack_end = ADDR(.stack);
|
||||
__stack_start = ADDR(.stack) + SIZEOF(.stack);
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
/* Unused exception related info that only wastes space */
|
||||
*(.ARM.exidx);
|
||||
*(.ARM.exidx.*);
|
||||
*(.ARM.extab.*);
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue