diff --git a/libboard_zynq/src/ddr/mod.rs b/libboard_zynq/src/ddr/mod.rs
index 51b20d7..b8ff935 100644
--- a/libboard_zynq/src/ddr/mod.rs
+++ b/libboard_zynq/src/ddr/mod.rs
@@ -316,7 +316,7 @@ impl DdrRam {
 
             for megabyte in 0..slice.len() / (1024 * 1024) {
                 let start = megabyte * 1024 * 1024 / 4;
-                let end = ((megabyte + 1) * 1024 * 1024 / 4);
+                let end = (megabyte + 1) * 1024 * 1024 / 4;
                 for b in slice[start..end].iter_mut() {
                     expected.map(|expected| {
                         let read: u32 = *b;