From aebce435e2e7120d79b218d21e8d7f2bbe02f057 Mon Sep 17 00:00:00 2001
From: Astro <astro@spaceboyz.net>
Date: Sun, 14 Jun 2020 23:49:17 +0200
Subject: [PATCH] mmu: switch bufferable=1 (writeback) for DDR pages

---
 libcortex_a9/src/mmu.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libcortex_a9/src/mmu.rs b/libcortex_a9/src/mmu.rs
index 2b998b8..ce48bec 100644
--- a/libcortex_a9/src/mmu.rs
+++ b/libcortex_a9/src/mmu.rs
@@ -132,7 +132,7 @@ impl L1Table {
                 domain: 0b1111,
                 exec: true,
                 cacheable: true,
-                bufferable: false,
+                bufferable: true,
             });
         }
         /* 0x40000000 - 0x7fffffff (FPGA slave0) */