From 4d3b2ac7e51c9e1d471bebf9daafe514001b57a6 Mon Sep 17 00:00:00 2001 From: Astro Date: Mon, 11 Nov 2019 00:06:35 +0100 Subject: [PATCH] zynq::ddr: use different data_bus_width for targets DDR still works only on the zc706, not on the cora z7-10. --- src/zynq/ddr/mod.rs | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/zynq/ddr/mod.rs b/src/zynq/ddr/mod.rs index bd27e19..fc65528 100644 --- a/src/zynq/ddr/mod.rs +++ b/src/zynq/ddr/mod.rs @@ -169,10 +169,14 @@ impl DdrRam { self.regs.ddrc_ctrl.modify(|_, w| w .soft_rstb(false) ); + #[cfg(feature = "target_zc706")] + let width = regs::DataBusWidth::Width32bit; + #[cfg(feature = "target_cora_z7_10")] + let width = regs::DataBusWidth::Width16bit; self.regs.ddrc_ctrl.modify(|_, w| w .soft_rstb(true) .powerdown_en(false) - .data_bus_width(regs::DataBusWidth::Width32bit) + .data_bus_width(width) ); while self.status() == regs::ControllerStatus::Init {}