From 261455877d145aa402d1a09e7798146f64b96d02 Mon Sep 17 00:00:00 2001
From: Astro <astro@spaceboyz.net>
Date: Wed, 6 Nov 2019 23:05:29 +0100
Subject: [PATCH] zynq::ddr: fix DDR 3x/2x setup, print clocks

---
 src/zynq/ddr/mod.rs | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/zynq/ddr/mod.rs b/src/zynq/ddr/mod.rs
index 282c114..bd27e19 100644
--- a/src/zynq/ddr/mod.rs
+++ b/src/zynq/ddr/mod.rs
@@ -42,8 +42,9 @@ impl DdrRam {
         let clocks = CpuClocks::get();
         println!("Clocks: {:?}", clocks);
 
-        let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;
+        let ddr3x_clk_divisor = ((DDR_FREQ - 1 + clocks.ddr) / DDR_FREQ).min(255) as u8;
         let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
+        println!("DDR 3x/2x clocks: {}/{}", clocks.ddr / u32::from(ddr3x_clk_divisor), clocks.ddr / u32::from(ddr2x_clk_divisor));
 
         slcr::RegisterBlock::unlocked(|slcr| {
             slcr.ddr_clk_ctrl.write(
@@ -64,6 +65,7 @@ impl DdrRam {
             .max(1).min(63) as u8;
         let divisor1 = (clocks.ddr / DCI_FREQ / u32::from(divisor0))
             .max(1).min(63) as u8;
+        println!("DDR DCI clock: {} Hz", clocks.ddr / u32::from(divisor0) / u32::from(divisor1));
 
         slcr::RegisterBlock::unlocked(|slcr| {
             // Step 1.