pca006132
/
nac3
forked from M-Labs/nac3
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

core: Fix missing changes for codegen tests 

Apparently the changes were dropped after rebasing.
This commit is contained in:
David Mak 2023-09-20 16:59:47 +08:00
parent 9e57498958
commit 3e430b9b40
1 changed files with 35 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

60
nac3core/src/codegen/test.rs
View File

@ -13,7 +13,10 @@ use crate::{
}, },
}; };
use indoc::indoc; use indoc::indoc;
use inkwell::OptimizationLevel; use inkwell::{
targets::{InitializationConfig, Target},
OptimizationLevel
};
use nac3parser::{ use nac3parser::{
ast::{fold::Fold, StrRef}, ast::{fold::Fold, StrRef},
parser::parse_program, parser::parse_program,
@ -182,23 +185,17 @@ fn test_primitives() {
; ModuleID = 'test' ; ModuleID = 'test'
source_filename = \"test\" source_filename = \"test\"
define i32 @testing(i32 %0, i32 %1) !dbg !4 { ; Function Attrs: mustprogress nofree norecurse nosync nounwind readnone willreturn
define i32 @testing(i32 %0, i32 %1) local_unnamed_addr #0 !dbg !4 {
init: init:
%add = add i32 %0, %1, !dbg !9 %add = add i32 %1, %0, !dbg !9
%cmp = icmp eq i32 %add, 1, !dbg !10 %cmp = icmp eq i32 %add, 1, !dbg !10
br i1 %cmp, label %then, label %else, !dbg !10 %. = select i1 %cmp, i32 %0, i32 0, !dbg !11
ret i32 %., !dbg !12
then: ; preds = %init
br label %cont, !dbg !11
else: ; preds = %init
br label %cont, !dbg !12
cont: ; preds = %else, %then
%if_exp_result.0 = phi i32 [ %0, %then ], [ 0, %else ], !dbg !13
ret i32 %if_exp_result.0, !dbg !14
} }
attributes #0 = { mustprogress nofree norecurse nosync nounwind readnone willreturn }
!llvm.module.flags = !{!0, !1} !llvm.module.flags = !{!0, !1}
!llvm.dbg.cu = !{!2} !llvm.dbg.cu = !{!2}
@ -213,15 +210,15 @@ fn test_primitives() {
!8 = !{} !8 = !{}
!9 = !DILocation(line: 1, column: 9, scope: !4) !9 = !DILocation(line: 1, column: 9, scope: !4)
!10 = !DILocation(line: 2, column: 15, scope: !4) !10 = !DILocation(line: 2, column: 15, scope: !4)
!11 = !DILocation(line: 2, column: 5, scope: !4) !11 = !DILocation(line: 0, scope: !4)
!12 = !DILocation(line: 2, column: 22, scope: !4) !12 = !DILocation(line: 3, column: 8, scope: !4)
!13 = !DILocation(line: 0, scope: !4)
!14 = !DILocation(line: 3, column: 8, scope: !4)
"} "}
.trim(); .trim();
assert_eq!(expected, module.print_to_string().to_str().unwrap().trim()); assert_eq!(expected, module.print_to_string().to_str().unwrap().trim());
}))); })));
Target::initialize_all(&InitializationConfig::default());
let llvm_options = CodeGenLLVMOptions { let llvm_options = CodeGenLLVMOptions {
opt_level: OptimizationLevel::Default, opt_level: OptimizationLevel::Default,
target: CodeGenTargetMachineOptions::from_host_triple(), target: CodeGenTargetMachineOptions::from_host_triple(),
@ -373,19 +370,23 @@ fn test_simple_call() {
; ModuleID = 'test' ; ModuleID = 'test'
source_filename = \"test\" source_filename = \"test\"
define i32 @testing(i32 %0) !dbg !5 { ; Function Attrs: mustprogress nofree norecurse nosync nounwind readnone willreturn
define i32 @testing(i32 %0) local_unnamed_addr #0 !dbg !5 {
init: init:
%call = call i32 @foo.0(i32 %0), !dbg !10 %add.i = shl i32 %0, 1, !dbg !10
%mul = mul i32 %call, 2, !dbg !11 %mul = add i32 %add.i, 2, !dbg !10
ret i32 %mul, !dbg !11 ret i32 %mul, !dbg !10
} }
define i32 @foo.0(i32 %0) !dbg !12 { ; Function Attrs: mustprogress nofree norecurse nosync nounwind readnone willreturn
define i32 @foo.0(i32 %0) local_unnamed_addr #0 !dbg !11 {
init: init:
%add = add i32 %0, 1, !dbg !13 %add = add i32 %0, 1, !dbg !12
ret i32 %add, !dbg !13 ret i32 %add, !dbg !12
} }
attributes #0 = { mustprogress nofree norecurse nosync nounwind readnone willreturn }
!llvm.module.flags = !{!0, !1} !llvm.module.flags = !{!0, !1}
!llvm.dbg.cu = !{!2, !4} !llvm.dbg.cu = !{!2, !4}
@ -399,15 +400,16 @@ fn test_simple_call() {
!7 = !{!8} !7 = !{!8}
!8 = !DIBasicType(name: \"_\", flags: DIFlagPublic) !8 = !DIBasicType(name: \"_\", flags: DIFlagPublic)
!9 = !{} !9 = !{}
!10 = !DILocation(line: 1, column: 9, scope: !5) !10 = !DILocation(line: 2, column: 12, scope: !5)
!11 = !DILocation(line: 2, column: 12, scope: !5) !11 = distinct !DISubprogram(name: \"foo.0\", linkageName: \"foo.0\", scope: null, file: !3, line: 1, type: !6, scopeLine: 1, flags: DIFlagPublic, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !4, retainedNodes: !9)
!12 = distinct !DISubprogram(name: \"foo.0\", linkageName: \"foo.0\", scope: null, file: !3, line: 1, type: !6, scopeLine: 1, flags: DIFlagPublic, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !4, retainedNodes: !9) !12 = !DILocation(line: 1, column: 12, scope: !11)
!13 = !DILocation(line: 1, column: 12, scope: !12)
"} "}
.trim(); .trim();
assert_eq!(expected, module.print_to_string().to_str().unwrap().trim()); assert_eq!(expected, module.print_to_string().to_str().unwrap().trim());
}))); })));
Target::initialize_all(&InitializationConfig::default());
let llvm_options = CodeGenLLVMOptions { let llvm_options = CodeGenLLVMOptions {
opt_level: OptimizationLevel::Default, opt_level: OptimizationLevel::Default,
target: CodeGenTargetMachineOptions::from_host_triple(), target: CodeGenTargetMachineOptions::from_host_triple(),