forked from M-Labs/artiq-zynq
79 lines
2.0 KiB
Rust
79 lines
2.0 KiB
Rust
#![no_std]
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#![no_main]
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#![recursion_limit="1024"] // for futures_util::select!
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#![feature(alloc_error_handler)]
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#![feature(panic_info_message)]
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extern crate alloc;
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use core::{cmp, str};
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use log::info;
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use libboard_zynq::{timer::GlobalTimer, logger, devc, slcr};
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use libsupport_zynq::ram;
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mod sd_reader;
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mod config;
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mod net_settings;
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mod proto_core_io;
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mod proto_async;
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mod comms;
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mod rpc;
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#[path = "../../../build/pl.rs"]
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mod pl;
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mod rtio;
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mod kernel;
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mod moninj;
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mod load_pl;
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mod eh_artiq;
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mod panic;
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fn identifier_read(buf: &mut [u8]) -> &str {
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unsafe {
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pl::csr::identifier::address_write(0);
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let len = pl::csr::identifier::data_read();
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let len = cmp::min(len, buf.len() as u8);
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for i in 0..len {
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pl::csr::identifier::address_write(1 + i);
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buf[i as usize] = pl::csr::identifier::data_read();
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}
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str::from_utf8_unchecked(&buf[..len as usize])
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}
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}
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#[no_mangle]
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pub fn main_core0() {
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let timer = GlobalTimer::start();
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let _ = logger::init();
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log::set_max_level(log::LevelFilter::Debug);
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info!("NAR3/Zynq7000 starting...");
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ram::init_alloc_linker();
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if devc::DevC::new().is_done() {
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info!("gateware already loaded");
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// Do not load again: assume that the gateware already present is
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// what we want (e.g. gateware configured via JTAG before PS
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// startup, or by FSBL).
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// Make sure that the PL/PS interface is enabled (e.g. OpenOCD does not enable it).
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.init_postload_fpga();
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});
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} else {
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// Load from SD card
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match load_pl::load_bitstream_from_sd() {
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Ok(_) => info!("Bitstream loaded successfully!"),
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Err(e) => info!("Failure loading bitstream: {}", e),
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}
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}
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info!("detected gateware: {}", identifier_read(&mut [0; 64]));
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unsafe {
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pl::csr::rtio_core::reset_phy_write(1);
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}
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info!("network addresses: {}", net_settings::get_adresses());
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comms::main(timer);
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}
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