forked from M-Labs/artiq-zynq
143 lines
4.9 KiB
Python
143 lines
4.9 KiB
Python
from migen import *
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from migen.genlib.fsm import FSM
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from migen_axi.interconnect import axi
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from artiq.gateware.rtio.dma import RawSlicer, RecordConverter, RecordSlicer, TimeOffset, CRIMaster
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AXI_BURST_LEN = 16
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class AXIReader(Module):
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def __init__(self, membus):
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aw = len(membus.ar.addr)
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dw = len(membus.r.data)
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alignment_bits = log2_int(AXI_BURST_LEN*dw//8)
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self.sink = stream.Endpoint([("address", aw - alignment_bits)])
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self.source = stream.Endpoint([("data", dw)])
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# # #
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eop_pending = Signal()
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self.sync += [
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If(self.sink.stb & self.sink.ack & self.sink.eop, eop_pending.eq(1)),
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If(self.source.stb & self.source.ack & self.source.eop, eop_pending.eq(0)),
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]
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self.comb += [
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membus.ar.addr.eq(Cat(C(0, alignment_bits), self.sink.address)),
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membus.ar.id.eq(0), # Same ID for all transactions to forbid reordering.
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membus.ar.burst.eq(axi.Burst.incr.value),
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membus.ar.len.eq(AXI_BURST_LEN-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...).
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membus.ar.size.eq(log2_int(dw//8)), # Width of burst: 3 = 8 bytes = 64 bits.
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membus.ar.cache.eq(0xf),
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membus.ar.valid.eq(self.sink.stb & ~eop_pending),
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self.sink.ack.eq(membus.ar.ready & ~eop_pending)
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]
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# UG585: "Large slave interface read acceptance capability in the range of 14 to 70 commands"
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inflight_cnt = Signal(max=128)
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request_done = Signal()
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reply_done = Signal()
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self.comb += [
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request_done.eq(membus.ar.valid & membus.ar.ready),
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reply_done.eq(membus.r.valid & membus.r.ready & membus.r.last)
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]
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self.sync += inflight_cnt.eq(inflight_cnt + request_done - reply_done)
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self.comb += [
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self.source.stb.eq(membus.r.valid),
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membus.r.ready.eq(self.source.ack),
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self.source.data.eq(membus.r.data),
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# Note that when eop_pending=1, no new transactions are made and inflight_cnt is no longer incremented
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self.source.eop.eq(eop_pending & membus.r.last & (inflight_cnt == 1))
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]
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class DMAReader(Module, AutoCSR):
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def __init__(self, membus, enable):
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aw = len(membus.ar.addr)
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alignment_bits = log2_int(AXI_BURST_LEN*len(membus.r.data)//8)
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self.submodules.wb_reader = AXIReader(membus)
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self.source = self.wb_reader.source
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# All numbers in bytes
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self.base_address = CSRStorage(aw, alignment_bits=alignment_bits)
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# # #
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enable_r = Signal()
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address = self.wb_reader.sink
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assert len(address.address) == len(self.base_address.storage)
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self.sync += [
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enable_r.eq(enable),
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If(enable & ~enable_r,
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address.address.eq(self.base_address.storage),
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address.eop.eq(0),
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address.stb.eq(1),
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),
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If(address.stb & address.ack,
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If(address.eop,
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address.stb.eq(0)
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).Else(
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address.address.eq(address.address + 1),
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If(~enable, address.eop.eq(1))
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)
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)
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]
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class DMA(Module):
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def __init__(self, membus):
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self.enable = CSR()
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flow_enable = Signal()
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self.submodules.dma = DMAReader(membus, flow_enable)
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self.submodules.slicer = RecordSlicer(len(membus.r.data))
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self.submodules.time_offset = TimeOffset()
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self.submodules.cri_master = CRIMaster()
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self.cri = self.cri_master.cri
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self.comb += [
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self.dma.source.connect(self.slicer.sink),
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self.slicer.source.connect(self.time_offset.sink),
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self.time_offset.source.connect(self.cri_master.sink)
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]
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(self.enable.re, NextState("FLOWING"))
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)
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fsm.act("FLOWING",
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self.enable.w.eq(1),
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flow_enable.eq(1),
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If(self.slicer.end_marker_found,
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NextState("FLUSH")
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)
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)
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fsm.act("FLUSH",
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self.enable.w.eq(1),
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self.slicer.flush.eq(1),
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NextState("WAIT_EOP")
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)
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fsm.act("WAIT_EOP",
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self.enable.w.eq(1),
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If(self.cri_master.sink.stb & self.cri_master.sink.ack & self.cri_master.sink.eop,
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NextState("WAIT_CRI_MASTER")
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)
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)
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fsm.act("WAIT_CRI_MASTER",
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self.enable.w.eq(1),
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If(~self.cri_master.busy, NextState("IDLE"))
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)
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def get_csrs(self):
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return ([self.enable] +
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self.dma.get_csrs() + self.time_offset.get_csrs() +
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self.cri_master.get_csrs())
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